Modifying SDR SDRAM core to use 512 Mbit memory

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ISSUE:

There is source code for SDR SDRAM cores posted on the Internet; it is possible to download this Verilog/VHDL code, synthesize it, and use it in an FPGA. I've looked at each one of these cores, but I think they are unsuitable for my project. The problem has to do with changing the address bus to use a particular SDRAM chip. Some of the values are "hard-coded" and are not easily adaptable to my project, or the core seems to be incomplete.

(1) Altera app note SDRAM controller
http://www.altera.com/products/i...

(2) Versatile memory controller
http://opencores.org/project,ver...

(3) HSSDRC
http://opencores.org/project,hssdrc

(4) Synthesizable SDR SDRAM controller
(Can't find the source code anymore)
http://opencores.org/websvn,file...

(5) SDRAM controller in VHDL
http://www.vlsiip.com/vhdl/sdram...

(6) Altera Quartus II ALTMEMPHY generator
(I have an academic license of the Altera ALTMEMPHY DDR controller, but I am working with SDR memory.)

PROBLEM:

I've created a custom circuit board with an Altera Cyclone IV FPGA and an SDRAM chip. The SDRAM chip is a Micron MT48LC32M16A2 (http://download.micron.com/pdf/d...). This is a 512 Mbit SDR SDRAM chip with 8 Meg x 16 x 4 banks. The row addressing of this chip is 13 bits (from A0 to A12), the bank addressing is BA0 and BA1, and the column addressing is A0 to A9.

I've attempted to modify core (4) above to interface with the MT48LC32M16A2 SDRAM. I believe that there are minimal changes required to the core. I've attempted to make some of these changes (primarily to sd_addx and the address interfacing code in hostcont.v).

I've written a testbench to read and write values into a model of SDRAM memory. From the Micron website, I've downloaded a Verilog model of the MT48LC32M16A2 SDR SDRAM. Unfortunately, using my testbench, I cannot access any more than the first memory location of the SDRAM.

I've written the testbench in Verilog, and I am using Icarus Verilog to compile and run the code. The waveforms are being viewed using gtkwave. I am compiling the testbench and the rest of the code using the following command:

(iverilog -o testbench -cfile_list.txt) && (vvp testbench -lxt2)

I've attached to this post a zip file containing my testbench (driver.v) and the associated files. The run.sh script can be used to compile and run the testbench.

I am wondering if anyone could suggest how I might modify this SDRAM core so that it can work with the Micron MT48LC32M16A2 SDR SDRAM.

Alternately, is there another core available that I can use with the Micron MT48LC32M16A2?

Can anyone make any suggestions? I don't want to write my own version of an SDR SDRAM core; I would prefer a drop-in solution.

I also think that purchasing a commercial core is out of the question, since I am only making one circuit board for a research project. In addition, I would like to have Verilog source code available so that I can simulate the code using Icarus Verilog.
However, I am open to the possibility of licensing one core just for my own personal project.

Can anyone suggest anything?

I could not use SRAM for my project since I require the storage of a lot of data, and I could not fit a large bank of SRAM chips on my circuit board (there was not enough space).

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There's also another SDR SDRAM core posted on the Icarus Verilog FTP server:

ftp://icarus.com/pub/eda/sdram_wb/

However, it appears that the rows and cols of the SDRAM are hard-coded into the controller. I don't know if this is applicable for my application.

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There's also another SDRAM core on OpenCores, but it does not seem to support a 512 MBit memory:

http://opencores.org/project,mem...

Moreover, it does not seem to be possible to set the number of rows and columns of the SDRAM using this core.

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After much work, I've now evaluated two freely-available additional SDRAM cores:

1) XESS Corporation SDRAM core (http://www.xess.com/projects/sdr...

2) Lattice Semiconductor reference design (http://www.latticesemi.com/dynam...)

The Lattice Semiconductor reference design seems to work well. Moreover, technical support from Lattice is very good, and help is available if this reference design needs to be modified for your hardware. The stipulation with use of the code is that you must run the code on Lattice hardware.

I will update this post after conducting more tests with the Lattice Semiconductor reference design.