Microchip Launches New Generation of 8-bit AVR® MCUs with Core Independent Peripherals

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Leon Heller G1HSM

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Interesting.

 

I've thought for a while that the newer PIC peripherals, certainly the CIP ones, are superior to the AVR ones but that the AVR core is superior to the PIC.

 

Now it looks like we might be starting to get the best of both worlds.

#1 This forum helps those that help themselves

#2 All grounds are not created equal

#3 How have you proved that your chip is running at xxMHz?

#4 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand." - Heater's ex-boss

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But that's just talking about ATtiny817/816/814/417 - we've been talking about them at length for weeks and some folks are just waiting for Atmel to deliver the Xplained boards for them. How is this actually news?

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What's I find interesting is the line...

 

Quote:

...and are the first tinyAVR® microcontrollers...

 

An AVR core bolted into something like a 16F1888XX peripheral set would be very interesting...

 

#1 This forum helps those that help themselves

#2 All grounds are not created equal

#3 How have you proved that your chip is running at xxMHz?

#4 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand." - Heater's ex-boss

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DIP packaged USB would be nice.

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clawson wrote:

But that's just talking about ATtiny817/816/814/417 - we've been talking about them at length for weeks and some folks are just waiting for Atmel to deliver the Xplained boards for them. How is this actually news?

 

I don't think that Atmel said that they were using PIC peripherals, though. I could be wrong.

Leon Heller G1HSM

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leon_heller wrote:

I don't think that Atmel said that they were using PIC peripherals, though. I could be wrong.

You're right, they didn't. But some peripherals have gotten CIP features, like the ADC which can automatically accumulate up to 64 samples.

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!!!

Its looks bad AVR Chip with Microchip LOGO!

 

 

শূন্য  - The ZeRo

Last Edited: Thu. Nov 10, 2016 - 04:45 AM
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Digi-Key has the 817 in stock.

Leon Heller G1HSM

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"Its looks bad AVR Chip wirh Microchip LOGO!"

 

Frightful indeed.

 

"We trained hard... but it seemed that every time we were beginning to form up into a team, we would be reorganized. I was to learn later in life that we tend to meet any new situation by reorganizing. And a wonderful method it can be of creating the illusion of progress while producing confusion, inefficiency and demoralization." Petronius Arbiter, approx. 2000 years ago.

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But that only implement a LP filter (AVG) , it's not like a buffer where you can read 64 samples, when you wake up. 

 

 

add:

But it's first time I see a price , so from about $0.5 , and for a chip with all this seems to be ok.

Now I hope that the C compilers can use the changed setup (memory mapped flash but not memory mapped registers), many things needs to be rewritten to use the changes.

 

Does any know if the new programming interface is a copy of a PIC interface? 

Last Edited: Wed. Nov 9, 2016 - 02:17 PM
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"Dare to be naïve." - Buckminster Fuller

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leon_heller wrote:
Digi-Key has the 817 in stock.

As it should be, right? ;)

Pricing and Availability

The new generation of 8-bit tinyAVR MCUs is available in mass production today in QFN and SOIC packaging.

A couple days ago Octopart only found the '817 kits.  

 

Same now.  Mouser has flavours on order but no delivery dates.

 

DigiKey has stock?!?  Maybe someone bought them all...

 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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But not akin to General Motors killing Pontiac.

 

"Dare to be naïve." - Buckminster Fuller

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Torby wrote:

"Its looks bad AVR Chip wirh Microchip LOGO!"

 

Frightful indeed.

Indeed!!

 

Jim

I would rather attempt something great and fail, than attempt nothing and succeed - Fortune Cookie

 

"The critical shortage here is not stuff, but time." - Johan Ekdahl

 

"If you want a career with a known path - become an undertaker. Dead people don't sue!" - Kartman

"Why is there a "Highway to Hell" and only a "Stairway to Heaven"? A prediction of the expected traffic load?"  - Lee "theusch"

 

Speak sweetly. It makes your words easier to digest when at a later date you have to eat them ;-)  - Source Unknown

Please Read: Code-of-Conduct

Atmel Studio6.2/AS7, DipTrace, Quartus, MPLAB user

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eRony wrote:
Its looks bad AVR Chip wirh Microchip LOGO!

Is that the first nail in the coffin for the "Atmel" name ... ?

 

 

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awneil wrote:
Is that the first nail in the coffin
I don't believe it's the first...

David (aka frog_jr)

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The history of chip design manufacturer is littered with companies that have come and gone. Some went bust; some were absorbed.

#1 This forum helps those that help themselves

#2 All grounds are not created equal

#3 How have you proved that your chip is running at xxMHz?

#4 "If you think you need floating point to solve the problem then you don't understand the problem. If you really do need floating point then you have a problem you do not understand." - Heater's ex-boss

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"some were absorbed"

 

Or were they "Assimulated"!    My apologizes to the BORG  q:-)

Click Link: Get Free Stock: Retire early! PM for strategy

share.robinhood.com/jamesc3274

 

 

 

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ki0bk wrote:
My apologizes to the BORG

lol

 

One phrase, from TNG, is: "We are the Borg. Your biological and technological distinctiveness will be added to our own. Resistance is futile."

Borg (Star Trek) - Wikipedia

https://en.wikipedia.org/wiki/Borg_(Star_Trek)

 emphasis mine

 

also

Your culture will adapt to service us.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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ki0bk wrote:
Or were they "Assimulated"!
I believe the Borg would have said "assimilated"; however, I believe you have coined a new word with appropriate meaning.

Assimulate: to take over by simulating the previous functions of an organism (not quite getting it right!).wink

 

Edit: Oh no! Does that get me banned?

David (aka frog_jr)

Last Edited: Wed. Nov 9, 2016 - 05:51 PM
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clawson wrote:

But that's just talking about ATtiny817/816/814/417 - we've been talking about them at length for weeks and some folks are just waiting for Atmel to deliver the Xplained boards for them. How is this actually news?

Press releases often have their own timing, but there is a small element of news, which is the price.

The good news is, it is not showing the 'go away' price increases made on other AVRs recently, the not quite so good news, is the price point is only average.

8 bit price leaders are companies like ST, SiLabs, Nuvoton, and the EFM8BB3 for example, has a lower price for 5x MHz (3v3), 2x FLASH, 4x RAM and with better 12b ADC/12b DAC.

 

The Tiny81x does have Peripheral Touch Controller (PTC), and has a SO14N package choice, and offers wide-vcc.

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One of the good things is that it has eeprom

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leon_heller wrote:
Digi-Key has the 817 in stock.

 

Sorry, they actually have the demo board. No chips.

Leon Heller G1HSM

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In addition to the

 

http://www.digikey.com.au/produc...

 

Digikey also has the XPro version listed at 3 times the price but zero availability.

 

http://www.digikey.com.au/produc...

 

... and no I don't yet know what "extras" justify the price difference.

 

Ross McKenzie ValuSoft Melbourne Australia

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I have not had time to check (and can't do it here), does the GCC compiler make use of 2 pointers to flash? (I don't expect it ever will move Y away from ram) 

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sparrow2 wrote:
I have not had time to check (and can't do it here), does the GCC compiler make use of 2 pointers to flash? (I don't expect it ever will move Y away from ram)
In what circumstance? I thought I could persuade it to use 2 flash pointers using this:

#include <stdio.h>
#include <avr/io.h>

const __flash uint8_t data1[] = { 1,3,5,7,9,11,13,15};
const __flash uint8_t data2[] = { 2,4,6,8,10,12,14,16};

int main(void) {
    int n = 0;

    DDRB = 0xFF;
    DDRC = 0xFF;
    while(1) {
        PORTB = data1[n];
        PORTC = data2[n];
        n++;
        if (n > 8) {
            n = 0;
        }
    }
    return 0;
}

But sadly it generates this...

    DDRB = 0xFF;
  7c:	8f ef       	ldi	r24, 0xFF	; 255
  7e:	87 bb       	out	0x17, r24	; 23
    DDRC = 0xFF;
  80:	84 bb       	out	0x14, r24	; 20

const __flash uint8_t data1[] = { 1,3,5,7,9,11,13,15};
const __flash uint8_t data2[] = { 2,4,6,8,10,12,14,16};

int main(void) {
    int n = 0;
  82:	80 e0       	ldi	r24, 0x00	; 0
  84:	90 e0       	ldi	r25, 0x00	; 0

    DDRB = 0xFF;
    DDRC = 0xFF;
    while(1) {
        PORTB = data1[n];
  86:	fc 01       	movw	r30, r24
  88:	e4 5a       	subi	r30, 0xA4	; 164
  8a:	ff 4f       	sbci	r31, 0xFF	; 255
  8c:	24 91       	lpm	r18, Z
  8e:	28 bb       	out	0x18, r18	; 24
        PORTC = data2[n];
  90:	fc 01       	movw	r30, r24
  92:	ec 5a       	subi	r30, 0xAC	; 172
  94:	ff 4f       	sbci	r31, 0xFF	; 255
  96:	24 91       	lpm	r18, Z
  98:	25 bb       	out	0x15, r18	; 21
        n++;
  9a:	01 96       	adiw	r24, 0x01	; 1
        if (n > 8) {
  9c:	89 30       	cpi	r24, 0x09	; 9
  9e:	91 05       	cpc	r25, r1
  a0:	94 f3       	brlt	.-28     	; 0x86 <main+0xa>
  a2:	ef cf       	rjmp	.-34     	; 0x82 <main+0x6>

So it seems pretty intent on using Z. But did you mean for 417/817 specifically? I don't have support here for that. (code above for mega16)

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The question is does it use LD instead of LPM, for the new chips.

 

with LD it can use X as a pointer to flash.

 

 

Last Edited: Thu. Nov 10, 2016 - 12:15 PM
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sparrow2 wrote:

The question is does it use LD instead of LPM, for the new chips.

 

with LD it can use X as a pointer to flash.

You can use both. The difference is that if you read PROGMEM with LPM you start addressing from 0x0000. If you use LD you start addressing from MAPPED_PROGMEM = 0x8000.

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But what does the compiler for 817 generate? Does it do LPMs ((a) because the memory addressing is "obvious" and (b) because that's what a __flash access would usually do) or does it "know" the 817 and do LDs (and hence have access to X, Y and Z)?

 

I don't have 817 support here so cannot try a test program.

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ok I will test it when I get home

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I took a copy and it make the same code as you show for a mega324.

 

but with a 817 as a target something are really wrong!

I use a studio7 downloaded about 1 week ago so it should be uptodate!

 

I get this :

Error        recipe for target 'main.o' failed    GccApplication4    c:\users\admin\Documents\Atmel Studio\7.0\GccApplication4\GccApplication4\Debug\Makefile    79

 

and in the make file it's 2. line if this part: 

./%.o: .././%.c
    @echo Building file: $<
    @echo Invoking: AVR/GNU C Compiler : 4.9.2
    $(QUOTE)C:\Program Files (x86)\Atmel\Studio\7.0\toolchain\avr8\avr8-gnu-toolchain\bin\avr-gcc.exe$(QUOTE)  -x c -funsigned-char -funsigned-bitfields -DDEBUG  -I"C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATtiny_DFP\1.1.102\include"  -O1 -ffunction-sections -fdata-sections -fpack-struct -fshort-enums -g2 -Wall -mmcu=attiny817 -B "C:\Program Files (x86)\Atmel\Studio\7.0\Packs\atmel\ATtiny_DFP\1.1.102\gcc\dev\attiny817" -c -std=gnu99 -MD -MP -MF "$(@:%.o=%.d)" -MT"$(@:%.o=%.d)" -MT"$(@:%.o=%.o)"   -o "$@" "$<" 
    @echo Finished building: $<

 

any idea ? 

 

 

 

Add

An "empty" project compile fine

 

 

Add 

this is more about studio 7

when I take the datasheet for a mega324P project it open mega32 !!!

is this really the quality of studio7 , just one hacked mess :( 

Last Edited: Thu. Nov 10, 2016 - 06:00 PM
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#include <stdio.h>
#include <avr/io.h>

const __flash uint8_t data1[] = { 1,3,5,7,9,11,13,15};
const __flash uint8_t data2[] = { 2,4,6,8,10,12,14,16};

int main(void) {
	int n = 0;

	PORTB.DIR = 0xFF;
	PORTC.DIR = 0xFF;
	while(1) {
		PORTB.OUT = data1[n];
		PORTC.OUT = data2[n];
		n++;
		if (n > 8) {
			n = 0;
		}
	}
	return 0;
}

gives (with -O1):

	PORTB.DIR = 0xFF;
  5c:	a0 e2       	ldi	r26, 0x20	; 32
  5e:	b4 e0       	ldi	r27, 0x04	; 4
  60:	8f ef       	ldi	r24, 0xFF	; 255
  62:	8c 93       	st	X, r24
	PORTC.DIR = 0xFF;
  64:	e0 e4       	ldi	r30, 0x40	; 64
  66:	f4 e0       	ldi	r31, 0x04	; 4
  68:	80 83       	st	Z, r24
	while(1) {
		PORTB.OUT = data1[n];
  6a:	81 e0       	ldi	r24, 0x01	; 1
  6c:	14 96       	adiw	r26, 0x04	; 4
  6e:	8c 93       	st	X, r24
		PORTC.OUT = data2[n];
  70:	82 e0       	ldi	r24, 0x02	; 2
  72:	84 83       	std	Z+4, r24	; 0x04
		n++;
  74:	81 e0       	ldi	r24, 0x01	; 1
  76:	90 e0       	ldi	r25, 0x00	; 0
	int n = 0;

	PORTB.DIR = 0xFF;
	PORTC.DIR = 0xFF;
	while(1) {
		PORTB.OUT = data1[n];
  78:	c0 e2       	ldi	r28, 0x20	; 32
  7a:	d4 e0       	ldi	r29, 0x04	; 4
		PORTC.OUT = data2[n];
  7c:	a0 e4       	ldi	r26, 0x40	; 64
  7e:	b4 e0       	ldi	r27, 0x04	; 4
	int n = 0;

	PORTB.DIR = 0xFF;
	PORTC.DIR = 0xFF;
	while(1) {
		PORTB.OUT = data1[n];
  80:	fc 01       	movw	r30, r24
  82:	e4 5c       	subi	r30, 0xC4	; 196
  84:	ff 4f       	sbci	r31, 0xFF	; 255
  86:	24 91       	lpm	r18, Z
  88:	2c 83       	std	Y+4, r18	; 0x04
		PORTC.OUT = data2[n];
  8a:	fc 01       	movw	r30, r24
  8c:	ec 5c       	subi	r30, 0xCC	; 204
  8e:	ff 4f       	sbci	r31, 0xFF	; 255
  90:	24 91       	lpm	r18, Z
  92:	14 96       	adiw	r26, 0x04	; 4
  94:	2c 93       	st	X, r18
  96:	14 97       	sbiw	r26, 0x04	; 4
		n++;
  98:	01 96       	adiw	r24, 0x01	; 1
		if (n > 8) {
  9a:	89 30       	cpi	r24, 0x09	; 9
  9c:	91 05       	cpc	r25, r1
  9e:	84 f3       	brlt	.-32     	; 0x80 <main+0x24>
			n = 0;
  a0:	80 e0       	ldi	r24, 0x00	; 0
  a2:	90 e0       	ldi	r25, 0x00	; 0
  a4:	ed cf       	rjmp	.-38     	; 0x80 <main+0x24>

 

 

Last Edited: Thu. Nov 10, 2016 - 07:57 PM
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so you make a 817 C project in studio 7 

and replace the code with cliffs.

 

And what else ?

 

As I say it works fine if I make a 324P  project and do the same. 

 

ok now I get it the structure needs to be like a xmega, and because of that X is waisted as a IO pointer, so it make it only worse than I had thought. 

 

Last Edited: Thu. Nov 10, 2016 - 08:37 PM
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At first glance, the program in #33 looks like a step back to e.g. early ARM "microcontrollers" which weren't known for "fast I/O".  But maybe not so bad. A feeling arose that in a full app, the index registers will wear out. ;)

 

So VPORT it is, then.  At least in these Tiny models, the three VPORTs let you map all of them:

There is room for a couple more before GPIO.  VPORTs and GPIOs are then in "low" I/O address space (SBI etc.), with CPU within range of IN/OUT.

 

The datasheet isn't clear to me -- is port A always mapped to Virtual Port A?  Or must configuration be done to select whic port is mapped to which virtual port, as in Xmega?

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

Last Edited: Thu. Nov 10, 2016 - 08:21 PM
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And here is the test I really was looking for: 

#include <stdio.h>
#include <avr/io.h>

const __flash uint8_t data1[] = { 1,3,5,7,9,11,13,15};
const __flash uint8_t data2[] = { 2,4,6,8,10,12,14,16};

int main(void) {
	int n = 0;

	PORTB.DIR = 0xFF;
	PORTC.DIR = 0xFF;
	while(1) {
		PORTB.OUT = data1[n]+data1[n+2];
		PORTC.OUT = data2[n];
		n++;
		if (n > 6) {
			n = 0;
		}
	}
	return 0;
}

and it insist on using LPM (only part of interest)

		PORTB.OUT = data1[n]+data1[n+2];
  80:	ac 01       	movw	r20, r24
  82:	44 5c       	subi	r20, 0xC4	; 196
  84:	5f 4f       	sbci	r21, 0xFF	; 255
  86:	9a 01       	movw	r18, r20
  88:	2e 5f       	subi	r18, 0xFE	; 254
  8a:	3f 4f       	sbci	r19, 0xFF	; 255
  8c:	f9 01       	movw	r30, r18
  8e:	34 91       	lpm	r19, Z
  90:	fa 01       	movw	r30, r20
  92:	24 91       	lpm	r18, Z
  94:	23 0f       	add	r18, r19
  96:	2c 83       	std	Y+4, r18	; 0x04

where it should have used ldd of Z so it only needed one pointer (because of known displacement).

 

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sparrow2 wrote:
where it should have used ldd of Z so it only needed one pointer (because of known displacement).

we'll have to see how Codevision attacks the beastie, given it has a different code generation model.  But I'll guess that in this type of example it won't do as good as GCC as it isn't as good on some "classic" optimizations.

 

You've got it set up -- can you try VPORT to see if it cleans up the I/O port work? 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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sparrow2 wrote:

ok now I get it the structure needs to be like a xmega, and because of that X is waisted as a IO pointer, so it make it only worse than I had thought. 

You can write it like this also, if it makes you feel better:

	PORTB_DIR = 0xFF;
	PORTC_DIR = 0xFF;
	while(1) {
		PORTB_OUT = data1[n];
		PORTC_OUT = data2[n];

Edit: typo

Last Edited: Fri. Nov 11, 2016 - 05:54 AM
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#38 that code make STS for the port same LPM, (but yes X isn't used)

 

#37 If I add V to the port things (VPORT_DIR etc) it will use OUT, (I'm not sure why it's not just on the IO addr, but I guess that this is a xmega's IO' and some controls just tied high or low )

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EDN wrote:

With this launch, Microchip says that it is reiterating both its intention to continue full support and development for ... AVR architecture; and its focus on 8bit. 

 

http://www.edn-europe.com/news/8...

 

Microchip wrote:

 Microchip is re-energizing new product development to not only continue to support, but to grow the esteemed AVR portfolio

From the press release cited in the OP: http://www.atmel.com/about/news/...

 

 

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Last Edited: Fri. Nov 11, 2016 - 08:18 AM
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I really can't get excited about this.

The way I2C is implemented in the atmega line is completely different from the attiny's and that's just plain annoying if you want to write a library.

Just as avr-libc. That library has 5 or more different variants?

 

And what about timers. I can understand a simple timer which is capable of hardly more than generating a system tick interrupt. I can also understand specialized timers for things such as 3-phase pwm with dead time insertion but the amount of different timer implementations in avr's just seems silly to me, even thou I also understand it's a result of almost 20 years of evolution.

 

Another clear example is the fuse bits. Atmel has made such a big mess of those with a one or zero in one place changing how other bits, written in a completely different part of the datasheet behave.

 

 

I haven't worked with microchip controllers since the good old 16f84 but I still have vague memories that they wrote their datasheets a lot clearer than atmel did.

I also like the idea of the arm datasheets (though they also have issues). First you get an description of a timer, including a bunch of pwm/ capture channels and then they say: Oh, by the way, this chip has 7 of these timers. (And then they still need 1300 pages for a datasheet for a small microcontroller (STM32F103C8T6) which is in the same price range as atmega's).

 

Over the years i've come to understand that writing software is not about typing code that "works", but much more about writing code that is easy understand, maintain & port.

it's easy to write code that has no obvious errors, but it's hard to write code that obviously has no errors.

 

It's 2016 now, we're not living in the '80 ies anymore. How many new functionality is there to add to microcontroller peripherals?

 

I can also see a future for the combination of microcontroller core + fpga. Adding fpga to the hardware is probably relatively expensive. I believe there is a uC fab which has reconfigurarable peripherals. uart, spi and i2c have most hardware in common. I avoid the attiny's (just because I don't want to learn the difference between the tiny's and the mega's). I believe the tiny's "usi" is an attempt in this direction, but at the glance I think they've at the same time simplified the usi so much that it's harder to use. How much real estate would it cost to do away with uart / spi / i2c peripherals and put 5 usi's in the silicon? Does a few flipflops for the peripherals really matter in comparison tho the FLASH & uC core?

 

Please Mr Microchip,

make the peripherals more alike, so sw developers can concentrate more on their job instead of wasting time on the minuscule periphal differences of the controller they happen to use in that particular week.

Doing magic with a USD 7 Logic Analyser: https://www.avrfreaks.net/comment/2421756#comment-2421756

Bunch of old projects with AVR's: http://www.hoevendesign.com

Last Edited: Fri. Nov 11, 2016 - 03:29 PM
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Paulvdh wrote:
Just as avr-libc. That library has 5 or more different variants?
It has SEVENTEEN variants (which is why people don't generally use lib.a on AVR!)

 

(thinks: presumably that 17 becomes 18 when you apply the 817 support pack?)

but the amount of different timer implementations in avr's just seems silly to me

So which of the 16 WGM modes do you think it is that has never been used?

Last Edited: Fri. Nov 11, 2016 - 02:10 PM
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Paulvdh wrote:

I really can't get excited about this.

.... I avoid the attiny's (just because I don't want to learn the difference between the tiny's and the mega's).

 

This new 817 series are 'tiny' in package branding only, it actually has more in common with the XMEGA, than anything else.

 

So you can use this, and still avoid "learn the difference between the tiny's and the mega's"

( but you may need to brush up on learn the difference between the mega's and the xmega's  ;)

 

Paulvdh wrote:

It's 2016 now, we're not living in the '80 ies anymore. How many new functionality is there to add to microcontroller peripherals?

There is still plenty of scope to improve peripherals :)

 

One of my peeves with 32b MCUs, is those that chose to include only 16b Timers.

Of course, they may have followed your wish of "make the peripherals more alike," but the down side of that, is a compromised performance.

One key reason to move to 32b is the wider dynamic range, and to use 16b timers is very limiting.

I think this is improving, as more users are like me, simply ignoring the poorly designed parts.

 

Paulvdh wrote:

I can also see a future for the combination of microcontroller core + fpga. Adding fpga to the hardware is probably relatively expensive. I believe there is a uC fab which has reconfigurarable peripherals. uart, spi and i2c have most hardware in common....

How much real estate would it cost to do away with uart / spi / i2c peripherals and put 5 usi's in the silicon?

Does a few flipflops for the peripherals really matter in comparison tho the FLASH & uC core?

FPGA has been tried and largely failed (AT94 anyone?), but there are Configurable Logic Cells appearing in MCUs, which are more like single-macrocells from CPLDs.

These can be quite useful, for doing operations missing from the standard peripherals.

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The AT94 could have been the chip to beat, but Atmel totally failed the tool support.  

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sparrow2 wrote:

The AT94 could have been the chip to beat, but Atmel totally failed the tool support.  

It was not just the tools, but also the price and market footprint.

The AVR has no external code and that severely limited the combinations possible.

 

FPGA and MPU do seem to have a footprint now, but it is with Xilinx and Microsemi and Altera offering higher end ARM cores, and larger FPGA fabric.

- not really in the Microcontroller space anymore.

 

Cypress have PSoC, which are more CPLD level logic, & those are more in the MCU space/package/price.

Last Edited: Fri. Nov 11, 2016 - 09:46 PM
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Ok I had a look at it so I changed the code from #36 to this :

 

#include <stdio.h>
#include <avr/io.h>

const __flash uint8_t data1[] = { 1,3,5,7,9,11,13,15};
const __flash uint8_t data2[] = { 2,4,6,8,10,12,14,16};

int main(void) {
	int n = 0;
	uint8_t *temp=(uint8_t *)data1 + 0x8000;;

	VPORTB_DIR = 0xFF;
	VPORTC_DIR = 0xFF;
	while(1) {
		VPORTB_OUT = *(temp+n)+*(temp+n+2);
		VPORTC_OUT = data2[n];
		n++;
		if (n > 6) {
			n = 0;
		}
	}
	return 0;
}

and it make this code: (only the part of interest)

		VPORTB_OUT = *(temp+n)+*(temp+n+2);
  66:	fc 01       	movw	r30, r24
  68:	e4 5c       	subi	r30, 0xC4	; 196
  6a:	ff 47       	sbci	r31, 0x7F	; 127
  6c:	32 81       	ldd	r19, Z+2	; 0x02
  6e:	20 81       	ld	r18, Z
  70:	23 0f       	add	r18, r19
  72:	25 b9       	out	0x05, r18	; 5

And that is very good, it use ldd so only one pointer value.

 

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Who-me wrote:
FPGA has been tried and largely failed

Anyone else remember the Triscend E5 (8051) and/or A5 (ARM) ?

E5 Customisable Microcontroller Block Diagram

http://antronics.co.uk/portfolio...

 

They didn't really get a chance to "fail" - Xilinx just bought them & killed the product.

 

Top Tips:

  1. How to properly post source code - see: https://www.avrfreaks.net/comment... - also how to properly include images/pictures
  2. "Garbage" characters on a serial terminal are (almost?) invariably due to wrong baud rate - see: https://learn.sparkfun.com/tutorials/serial-communication
  3. Wrong baud rate is usually due to not running at the speed you thought; check by blinking a LED to see if you get the speed you expected
  4. Difference between a crystal, and a crystal oscillatorhttps://www.avrfreaks.net/comment...
  5. When your question is resolved, mark the solution: https://www.avrfreaks.net/comment...
  6. Beginner's "Getting Started" tips: https://www.avrfreaks.net/comment...