This is a weird one for me. It's not like I've never used pin-change interrupts over the years, and sometimes as critical parts of the app.
A four-channel "signal processing" app with a Mega164. Original boards had ATmega164PV-10AU. Also tried were A and PA with the same symptoms as below. 5V; 7.37MHz.
Each input channel has a small daughter board to handle a variety of input signals. The module in question handles 0-5VDC, 0-10VDC, 4-20mA, and pulse inputs from a flowmeter--typically up to 100Hz full-flow.
(Below, "protdiode" refers to DLPT05 "TVS DIODE 5VWM 9.8VC SOT23-3" to/from rails)
Rough description of signal chain: input terminal -- gain resistors -- RC -- opamp -- protdiode -- main board -- protdiode -- RC -- ADCpin.
The four input channels go to ADC pins PA0-PA3. I'm set up to do continuous round-robin ADC conversions on the four channels, with an ADC clock of 57.6kHz, and conversion-complete ISR that starts the conversion on the next channel. I've done this on many many AVR production apps.
To address the flowmeter "Hz" input, I sez to myself: "Self, let's do a bank of pin-change, with a mask for the channel(s) that are configured as Hz inputs."
Fire up the code, and the Hz input and processing and display worked--except that the Hz value is about 15% too high. Further instrumentation and inspection with 'scope and such indicates that there are spurious pin-change hits. A 100Hz input signal expects 200 pin change hits per second. Actual is about 230.
Indeed, due to the RC the falling edge has a time constant. But the time to fall between e.g. logic high and logic low is fast enough--about 50us to 100us. The signal looks dead clean on a 'scope trace. Right at the AVR pin.
NOW HERE IS THE FUN PART:
Let's take the PA0 channel that is getting 230 when 200 is expected. If the ADC operation is changed so that no conversions are done on ADC0, the symptoms [mostly] go away. Instead of about 30 extra hits every second, it drops to a spurious hit every 5 to 10 seconds.
The 'A seems marginally better than the 'PV.
I've convinced myself that there is "something" inside the AVR, at least on this model series, where pin-change is affected by ADC. I'd speculate that during the sample-and-hold on PA0 it affects the pin-change internal level somehow.
All speculation. Any other ideas?
I'm going to fall back to fast-poll of the signals...