This prob has had me stumped for days. I have a buildtoprint of a mega128 bd we built back in 03 (!) that uses a ram and the extmem interface. It has a 74LS373 latch and a 138 decoder with chip selects going to a CS8900 eth chip, a kbd encoder chip, and an lcd display chip. When I burn the prog using the jtagice, program runs perfect. Then I disconnect power and repower, and it acts like the ext mem interface isnt initing. The clue is, when you dump the address where the eth chip is, you get incrementing bytes on the bus read. I print out the contents of 0x230a and b and when its initialized right, I see 0x630e (contents of reg0 in the chip). When it not working, I see 0d0c like the memdump at 0x2300. When its working, the eth chip inits and reads and writes ok, the kbd chip works, the display works, the ram works (holds the display stuff). I have it rigged to spin in a loop reiniting everything and after a couple secs, it sticks... good numbers show up on the screen. At first, it would always init ok if I hit the hw reset button. It acts like a cap charging up. I'm scopeing everything... power pins, chip selects. Hitting the hw resets starts it in the reinit loop. Doesnt matter if the jtag is connected or not. Doesnt matter if the jtag is disabled or not at init. The hw reset DOES NOT go to the CS8900. I send it a sw init. I guess it just isnt getting a good poweron reset. (Thanks for reading.... I'll add a delay before the 1st init... standby...) post any additional suggested tests... thanks. Crap. Adding 300ms delay at poweron before swinit didnt make it better. Its a 4 layer bd with pwr and gnd in the middle, and every chip and cap has vias down to pwr and gnd.