Mega 0-Series and TWI (ATMEGA4808)

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I'm trying to implement TWI Master on a ATMEGA4808 

The device is a superb device, very rich on features, but the datasheet makes understanding thw TWI interface quite hard!

 

First the problem...

I'm trying read register 0 on a TAS5575M which is at address 0x34 (7 bit address)

I seem to be able to send the address byte with read-btit set no problem, but then nothing...

 

Here's my setup code:

static volatile uint8_t dummy_u8;

void i2c_master_init(void)
{
	PORTMUX.TWISPIROUTEA=PORTMUX_TWI0_DEFAULT_gc;
	TWI0.MBAUD = 70;
	TWI0.MCTRLB |= TWI_FLUSH_bm;
	TWI0.MSTATUS |= (TWI_RIF_bm | TWI_WIF_bm);
	
	i2c_master_enable();
}

void i2c_master_enable()
{
	TWI0.MCTRLA = TWI_ENABLE_bm;
	TWI0_MSTATUS |= TWI_BUSSTATE_IDLE_gc;
}

 

And then I send a start using this (sending 0x34 as the address):

uint8_t i2c_master_start(uint8_t addr)
{
	if ((TWI0.MSTATUS & TWI_BUSSTATE_gm) != TWI_BUSSTATE_BUSY_gc)
	{
		TWI0.MCTRLB &= ~(TWI_ACKACT_bm);
		TWI0.MADDR = addr;
		
		if (addr & 0x01)
		{
			// wait for RIF which means the ADDR byte in read mode has been sent.
			while (!(TWI0_MSTATUS & TWI_RIF_bm));
		}
		else
		{
			while (!(TWI0_MSTATUS & TWI_WIF_bm));
		}
		return TWI0.MSTATUS;
	}
	else
	return TWI0.MSTATUS;
}

 

And then I try to send the register address using this, with 0x00 as the data:

uint8_t i2c_master_write(uint8_t data)
{
	if ((TWI0.MSTATUS & TWI_BUSSTATE_gm) == TWI_BUSSTATE_OWNER_gc)
	{
		dummy_u8 = TWI0_MSTATUS;
		TWI0.MDATA = data;
		
		while(1)
		{
			dummy_u8 = TWI0_MSTATUS;
			if(dummy_u8 & TWI_WIF_bm)
			{
				break;
			}
		}
		
	}

	return TWI0.MSTATUS;
}

Now it just hangs in the while loop and MSTATUS stays stubbornly stuck at 0x22 

 

If I add a break point, so that it stops immedaitely after line "TWI0.MADDR = addr;" in i2c_master_start(), ie immediately after sending the Address Byte with Read Bit, my logic analyzer shows me this :

Which seems to be (almost) correct for a Read from a device at 0x34 - but what are all those extra clocks?

 

A logic anyalser screen catch

 

So not sure what is going on!

Anyone got any working TWI Master code for the 0-series I can compare with?

 

SpiderKenny
@spiderelectron
www.spider-e.com

 

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There's been previous threads about TWI on these AVR-0/1's previously - did you find them? I'm pretty sure one had a complete implementation.

 

BTW Microchip have a load of example drivers as documented here:

 

https://www.avrfreaks.net/forum/getting-started-attiny-1-0-series-application-notes

 

But TWI is notable by its absence from that.

 

EDIT: I should learn to read - #1 has more recently been updated to now include an I2C attachment.

Last Edited: Thu. Nov 7, 2019 - 05:17 PM
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Fab thanks - I'll check it out.

SpiderKenny
@spiderelectron
www.spider-e.com

 

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https://www.avrfreaks.net/commen...

this thread has what your looking for....

 

 

Jim

 

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ki0bk wrote:

https://www.avrfreaks.net/commen...

this thread has what your looking for....

 

 

Jim

 

Indeed. Thanks!

SpiderKenny
@spiderelectron
www.spider-e.com

 

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Have look my example in projects (assembler only)
https://community.atmel.com/projects/avr-megatiny-series-01-twi-master-sensor-hyt271
Maybe it helps

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GermanFranz wrote:

Have look my example in projects (assembler only)
https://community.atmel.com/proj...
Maybe it helps

 

Hi yes I saw that - seems specific to that sensor - but is a great help in me understanding how the 0-seris TWI works. Thanks!

 

Many thanks,

Kenny.

SpiderKenny
@spiderelectron
www.spider-e.com

 

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SpiderKenny wrote:

If I add a break point, so that it stops immedaitely after line "TWI0.MADDR = addr;" in i2c_master_start(), ie immediately after sending the Address Byte with Read Bit, my logic analyzer shows me this :

Which seems to be (almost) correct for a Read from a device at 0x34 - but what are all those extra clocks?

 

A logic anyalser screen catch

 

So not sure what is going on!


A bit late for this discussion I know, but I also was puzzled by the behaviour of TWI after starting a Read transaction. According to figure 24-13 in the megaAVR0 data sheet, there is no driver software interaction hold point after receiving the slave ack, the TWI module will automatically start clocking in the slave response. The m328p (as an example of a classic atmega) in contrast requires the software to set the necessary bits in TWCR to start the read transaction.

Last Edited: Fri. Nov 15, 2019 - 05:43 PM