Since I released my first AVR bit-bang UART several years ago, I've had a number of requests for interrupt-driven receive. For the best accuracy, an interrupt-driven bit-bang rx routine needs to factor the response time from the beginning of the start bit until the interrupt code runs. Since the the datasheet is unclear about the operation of the pin change interrupt synchronizers, I decided to do some testing on the t13 and t85 before writing the interrupt-driven receive code. I determined that the PCINT latency is 2 cycles longer than INT0, but only when the CPU clock is running. For any sleep mode, the synchronizer is not active.