max clock before the prescaler UC3A0512

1 post / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

The hunt for a fpll-out limit for UC3A0512:

In the datasheet fig.13-3 (PLL and optional divide by 2), the naming convention is:
fvco is the raw output from the VCO, 80-240MHz.
fpll is the output of the optional divide by 2, 40-? MHz.
PLLclock is fpll after a masking register.
Further, table 13-6 agrees with this. All good.

There's just one little comment on the bottom of page 55 that triggers my hunt for more data:

"To make the PLL output frequencies under 80 MHz the OTP[1] bitfield could be set. This will divide the output of the PLL by two and bring the clock in range of the max frequency of the CPU"

Hmm. If 'CPU' meant the processor this can also be accomplished using the divider in the sync clock generator. If 'CPU' really refers to the part, and specifically the fanout after the masking register to the divider blocks, this makes sense. Fast forward to the electrical characteristics.

From 38-10 we can infer that, since the PLL is allowed to run "80-240MHz", this figure is the fvco limit, not the fpll limit. The lower fpll limit has to be 40MHz due to the divider.

Since fvco is good to 240MHz, fpll is good to at least 120MHz. But what about 132? Do I need new glasses?

/Kasper