Major bug found in XMEGA waveform generation

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I found a hardware bug in XMEGA timer, When I was writing a sample code for activation of single slope PWM.
I wrote to atmel:

Quote:
There is problem in single slope PWM waveform generation. When TCC1.PER=255 and TCC1.CCBBUF=255, there is a very narrow periodic low pulse on PC5. By setting TCC1.PER=254 this narrow pulse disappears. But according to XMEGA documents, PC5 must be high in all of times when TOP value is equal to compare value. I saw this problem in ÙŽATXMEGA64A3 and ATXMEGA128A1 series.

Atmel replied:
Quote:
Dear customer,

I've verified the issue you see here also. There is a bug in the device and I've reported it to the design engineers.

For some reason it seems that the compare is offset by 1. So when the compare and period is equal, there is a negative pulse. But setting the compare to TOP+1, the negative pulse disappear.

I've tested this with the low values also, and to be able to have only a low output, the compare value have to be "1" (BOTTOM+1). When setting it to "0", there is a positive pulse on the line.

I'm sorry for the trouble this may have caused you. In the meanwhile you would need to implement a workaround by having the compare value go from 1 to 255, and the period/count is running from 0 to 254. As this is a 16-bit timer, you can also use compare from 1 to 256 and period at 255 if you like to maintain your resolution.

Hopefully the bug can be fixed for the next revision of the devices.


I will also test the possible bug in dual slope pwm mode and I will report the result here.

Ozhan KD
Knowledge is POWER

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Reply modified by Atmel:

Quote:
Disregard the bug about the bottom values not being correct. I mixed the probes when I measured compare channel A and B, so there is no bug on the bottom values.

The top value for compare is still a bug as I can see. Either this is a bug in the device, or the documentation of how it is supposed to work is wrong.

Ozhan KD
Knowledge is POWER

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Well we can expect this make it into the errata in about 6 months.

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I'm still waiting for an errata on a Atmel 8051 error found in 1997 :(

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I did some tests on dual slope pwm generation and the problem does not exist in this mode.

Ozhan KD
Knowledge is POWER

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After 3 years, I tested AU series and the problem is still present. When PER and CCx are equal in SS pwm mode, moving from BOTTOM to BOTTOM+1 makes pwm output high for one cycle. If CCx is greater than PER, output is high for all of the cycle and the single cycle high period disappears.

Ozhan KD
Knowledge is POWER

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This behavior is also present in mega avr timers in another form. From mega32 datasheet:

Quote:
If the OCR1x is set equal to BOTTOM (0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the OCR1x equal to TOP will result in a constant high or low output (depending on the polarity of the output set by the COM1x1:0 bits.)

Thus this single cycle spike appeares in XMEGA when CCx is equal to TOP and for avr it appears when OCRx is zero. Both cases do not seem to behave correctly as a single slope pwm generator.

Ozhan KD
Knowledge is POWER

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At least the limitation is described in the Mega spec sheets.

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net