I found a hardware bug in XMEGA timer, When I was writing a sample code for activation of single slope PWM.
I wrote to atmel:
There is problem in single slope PWM waveform generation. When TCC1.PER=255 and TCC1.CCBBUF=255, there is a very narrow periodic low pulse on PC5. By setting TCC1.PER=254 this narrow pulse disappears. But according to XMEGA documents, PC5 must be high in all of times when TOP value is equal to compare value. I saw this problem in ÙŽATXMEGA64A3 and ATXMEGA128A1 series.
I've verified the issue you see here also. There is a bug in the device and I've reported it to the design engineers.
For some reason it seems that the compare is offset by 1. So when the compare and period is equal, there is a negative pulse. But setting the compare to TOP+1, the negative pulse disappear.
I've tested this with the low values also, and to be able to have only a low output, the compare value have to be "1" (BOTTOM+1). When setting it to "0", there is a positive pulse on the line.
I'm sorry for the trouble this may have caused you. In the meanwhile you would need to implement a workaround by having the compare value go from 1 to 255, and the period/count is running from 0 to 254. As this is a 16-bit timer, you can also use compare from 1 to 256 and period at 255 if you like to maintain your resolution.
Hopefully the bug can be fixed for the next revision of the devices.
I will also test the possible bug in dual slope pwm mode and I will report the result here.