Low voltage on logic high

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#1
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Hello,

I've got an interesting issue with logic high. Ive got an ATmega644, 44pin package.

Ive got a chunk of simple code (among a lot of other code):

#define oc0STRT 0
#define oc1ACC1 1
#define oc2ACC2 2
#define oc3LOCK 3
#define oc4ULCK 4

...

	DDRC	= 0;
	DDRC	|= (1<<oc0STRT) | 
			   (1<<oc1ACC1) | 
			   (1<<oc2ACC2) | 
			   (1<<oc3LOCK) | 
			   (1<<oc4ULCK);
	PORTC	|= (1<<PINC5) |
			   (1<<PINC6) |
			   (1<<PINC7);

...

init();
	
	PORTC |= (1<<oc0STRT);
	PORTC |= (1<<oc1ACC1);
	PORTC |= (1<<oc2ACC2);
	PORTC |= (1<<oc3LOCK);
	PORTC |= (1<<oc4ULCK);
	while(1);

These outputs are driving npn transistor gates which drive relays.

Some work, some dont though:

if I probe:
pin c0: 5V
pin c1: 5V
pin c2: 1.1V
pin c3: 1.1V
pin c4: 1.1V

There are no short between neighboring pins, and the resistance between each respective pin and: ground, 5V, and input gate: are all the same.

Any clues on this one?

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Maybe JTAG enabled (PC2..PC5)?
- Check the JTAGEN fuse or
- set JTD in MCUCR (twice within 4 clock cycles).

/Martin.

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Those are JTAG pins.

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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How are the npn transistor configured, and what type of transistors are they?

If their emitters are tied to ground and you are driving their bases without any additional resistors, you won't see much more than a volt before their base-emitter junctions blow up :)

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Ive never used JTAG and I dont know why it would have been enabled when i opened it out of the package.
good work guys!

...albeit I feel a little dumber now :) (...and actually a little smarter too)

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Quote:

I dont know why it would have been enabled

JTAG is not only a debug interface but also a potential programming interface. So when you get a brand new chip out of the packet you have a choice of first programming it (setting fuses etc) with ISP or JTAG. Now some people layout boards with only ISP and some with both ISP and JTAG but if you own a JTAG interface the temptation is to only put a JTAG connection on the board as you can do everything that is done by ISP using it AND you can use it for debug. So when I've made (or had made) boards with AVR-JTAG chips in the past I've generally only had JTAG included (it's too useful not to use it if you can!). As such it'd be important for someone like me that virgin chips come with JTAG enabled so that's exactly what Atmel do - they ship such chips with both SPIEN and JTAGEN fuses activated.

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the more you know. good point. I guess if ISP wasnt enabled then I might be a bit of a pickle! touche!

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Quote:

I guess if ISP wasnt enabled then I might be a bit of a pickle! touche!

This is the reason you cannot change SPIEN using ISP - you cannot pull the rug from under its own feet. However I believe you can disable both SPIEN and JTAGEN using JTAG which can make the chip pretty tricky to contact!