LOw power SRAM accesses

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Does anyone know whether the AVR (namely ATmega1281) switches the high order addresses A15:A8 to match internal addresses if it accesses something internal?

Here's the problem: I need zero wait state operation with external SRAM, but also I want the SRAM to go into low standby current mode when not in use.

If the processor keeps the previous address active on the bus, the CS# will be active even if the processor is accessing internal memory, and I can't afford to wait for RD# or WR# to go low as I would need very fast access times to achieve zero wait state. I can't rely on ALE going active either, it might not.

My thoughts: I'm using a PLD for address decoding, so I can theoretically turn off the SRAM CS# signal at the end of the cycle using logic, but override this if another ALE is seen with another SRAM address.

Anyone done something similar?

Thanks!

Mark.

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Check out section 9.1.1 of the ATmega1281 datasheet, pages 27-28.

Quote:
When the XMEM interface is enabled, also an internal access will cause activity on address, data and ALE ports, but the RD and WR strobes will not toggle during internal access.

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Whoops, missed that! Thanks. This is very good news, I've got access to all the addresses in the PLD and can actually decode whether it is an SRAM address or not. All I have to do now is figure out how to force all data and hardware stack accesses to internal RAM and put those data structures that are accessed most often there too.