Does anyone know whether the AVR (namely ATmega1281) switches the high order addresses A15:A8 to match internal addresses if it accesses something internal?
Here's the problem: I need zero wait state operation with external SRAM, but also I want the SRAM to go into low standby current mode when not in use.
If the processor keeps the previous address active on the bus, the CS# will be active even if the processor is accessing internal memory, and I can't afford to wait for RD# or WR# to go low as I would need very fast access times to achieve zero wait state. I can't rely on ALE going active either, it might not.
My thoughts: I'm using a PLD for address decoding, so I can theoretically turn off the SRAM CS# signal at the end of the cycle using logic, but override this if another ALE is seen with another SRAM address.
Anyone done something similar?