Lock bits and LPM & SPM

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Device: ATMEGA64
Recently my code size grew so big that I only have a couple of bytes remaining in flash.
Normally I would program the BLB0 and BLB1 as follows:

BLB0: LPM and SPM prohibited in Application Section
BLB1: LPM prohibited in boot section.

I have no boot loader code. But my code has always been so large that it flowed into the boot loader flash area.

Now that I have very little flash remaining, these settings fail. Why?

Without these settings, I guess the LPM and SPM instruction are now able to be executed...should I be concerned?

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LPM in boot section is fine.
You should prohibit SPM in the boot section.

All the same, why worry?

Lockbits will deter most people, most of the time.

If you are paranoid, you can always top yourself.

David.

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If you do not use a bootloader section == you do not program flash at run-time,
then disable spm in both bootloader and application sections. That is the safest option.
By the way, any ATMega128 around?

No RSTDISBL, no fun!

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I think you missed my question.
Studio fails when I attempt to lock the LPM and SPM.

ISP MODE ERROR (window)

A problem occured when executing the command, make sure that you are using the correct programming method ....

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I have the boot size set to the lowest size of 512 words. I suspect that the code grew into this space and now, for reasons I don't understand, the LPM and SPM instructions can no longer be blocked.
I guess my concern is if the code goes into the weeds and ends up executing an instruction from unused flash space, it may translate to a SPM and corrupt flash.
If unused flash is explicitly set to a value that is a nop or the like, then I suppose I have no issue.

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Quote:

If unused flash is explicitly set to a value that is a nop or the like, then I suppose I have no issue.

Aah, now >>that<< is something that can generate a lot of discussion:
https://www.avrfreaks.net/index.p...
https://www.avrfreaks.net/index.p...
and follow links therein.

Quote:

it may translate to a SPM and corrupt flash.

So, the rogue sequence will just happen to set SPMEN in SPMCR, and load SPMCR with PGWRT or other similar value, and Z will just happen to have a valid page address, AND the SPM will occur within 4 clock cycles of the above.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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I found that it was prohibiting the LPM that was the issue. Although I thought I had tried it before without success, just prohibiting the SPM works.