My symply project for using ATTiny2313A-20PU and 74LS138N with LED display with common cathode for control LM7001M (dummy edition , without memory save and channel switching, using only 'f+' and 'f-' on pins 2 and 3 ).
Prototype of the code is http://vrtp.ru/index.php?act=Attach&type=post&id=440354 (from Internet ,prototype is not my project), modifyed for led with common cathode, may be rebuilded for 5... 6 digits, 3... 5 buttons.
V2.05_mem.zip (367.92 KB) - version for memory read button, step control , IF constant was patched for IF filter , BQ 7.2 MHz and AFC of tuner . Using with 10 uF ,27 Ohm and 0.8...1,5kOhm in the amplifier-integrator.
V208.zip with circuit and hex for 5 buttons, 1 memory preset , advanced circuit , IF 10.7 MHz , Fosc>Fsig,internal RC osc 4MHz,LEDs
For modify step replace data in "Send8Bit(0b10000000);" in the subroutine and change types of data for Fcounter, change subroutines for LED out , memory
saveing and frequency increment/decrement :
if(ifmode==1 )
{
SPI_CE_PORT |= (1<<CE_PIN);
Send8Bit((DIVISOR +IF_VAL) & 0xFF);//D7...D0
Send8Bit(((DIVISOR +IF_VAL ) >> 8) & 0xFF); //T2=0,T1=0; D13...D8; or replace & 0xFF mask using &0b00111111(T2=0,T1=0; ) or &0x3f mask
Send8Bit(0b10000000); //byte=(S<<7|R2<<6|R1<<5|R0<<4|TB<<3|B2<<2|B1<<1|B0<<0)
PORTA = 0;
PORTD&=~(1<<CE_PIN);
}
//divisor=(fsig-fif)/fref
//divisor=(145500-10700)/25=5394
//divisor=(100800+10700)/100=1115
//data=D0;D1;D2;D3;D4;D5;D6;D7;D8;D9;D10;D11;D12;D13;T0;T1;B0;B1;B2;TB;R0;R1;R2;S;
//or control=(S<<7|R2<<6|R1<<5|R0<<4|TB<<3|B2<<2|B1<<1|B0<<0)
data for patching Send8Bit(control);
0b10000000 for step 100 kHz ,FMIn
0b11000000 for step 50 kHz ,FMin
0b10100000 for step 25kHz,FMin
0b11100000 for step 5 kHz,FMin ( it may not work for some freq.)
0b01100000 5kHz ,AMin
0b00010000 10kHz,AM in
0b01010000 9kHz ,AMIn
0b01110000 5kHz ,AMin
0b00110000 1kHz ,AMin
Send8Bit( ... ); Send8Bit( ... ); Send8Bit( ... );
D0;D1;D2;D3;D4;D5;D6;D7 ;D8;D9;D10;D11;D12;D13; T0;T1; B0;B1;B2;TB;R0;R1;R2;S;
1 ;1 ; 1 ; 1; 0 ; 1 ; 1 ; 1 ; 1 ; 1 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; control FMin divisor 1007
x ; x ; x ; x ; 1 ; 0 ; 0 ; 0 ; 1 ; 0 ; 0 ; 1 ; 0 ; 0 ; 0 ; 0 ; control AMin divisor =145 (fit data in subroutine )
R0 R1 R2 fref [kHz] BO1 BO2 BO3
0 0 0 100 1 1 0
0 0 1 50 1 1 0
0 1 0 25 1 1 0
0 1 1 5 0 0 1
1 0 0 10 1 0 1
1 0 1 9 1 0 1
1 1 0 1 0 1 1
1 1 1 5 0 0 1
Input Output
B0 B1 B2 TB nBO1 nBO2 nBO3
0 0 0 0 * * *
0 0 1 0 0 0 1
0 1 0 0 0 1 0
0 1 1 0 0 1 1
1 0 0 0 1 0 0
1 0 1 0 1 0 1
1 1 0 0 1 1 0
1 1 1 0 1 1 1
0 0 0 1 TB * *
5 1 0 1 TB 1 0
5 0 1 1 TB 0 1
5 1 1 1 TB 1 1
1 0 0 1 TB 0 0
S: Divider selection data
1: FMIN, 0: AMIN
If it is necessary, patch TB<<3|B2<<2|B1<<1|B0<<0 in the control byte using datasheet and use control|=(TB<<3|B2<<2|B1<<1|B0<<0) for BOx input
Photo0081.jpg (356.78 KB) circuit of tuner with TEA5711
MC3362DW.pdf (288.33 KB) MC3362 datasheet (tuner 27 MHz, tuner 145,6 MHz for amateur radio )
V211.zip for step 25 kHz, ATTiny2313A/ATTiny4313,6 digits (may be with some bugs, check and modify source .c codes )
V211_01.zip (897.71 KB) for fosc<fsignal
V211_tx.zip (897.63 KB) for Fif=0 (TX)
V215_ATTiny4313_plus.zip (911.86 KB) Version LM7001_pll.atsln for Atmel studio 7 , ATTiny4313,4MHz RC internal osc , no CKDIV8, (converted from .aps, no place in MCU, may be with bugs)
