For 3.3V output dsps i can drive the TTL loads as they are more tolerant. But as my application must be noise immune, CMOS seems to have better noise blocking
capacity.
What would you recommend ? Using 3.3V to TTL or using 3.3V + level shifter to CMOS?
I should also investigate if the level shifters are flexible enough (only input or bidirectional etc.)
Well, its not that TTL is "more tolerant". Take a look at the spec'd logic levels for TTL. Logic high with a 5v supply is typically 2.7V but can tolerate up to (almost) 5V. So it is actually a good match to 3.3V CMOS.
However, I would NOT design TTL into a new design unless I was forced to by factors beyond my control, such as a boss who says "you must...". If noise is a problem, take care of the noise, keep it out. Then your circuit will be happy.
Jim
Sorry I dont I meant TTL is more tolerant to noise , I mean TTL has more tolerant voltage range 2V..5V. Through this large range it is less immune to noise.
if the output is 3.3V cmos and the input is 5V (most gate drivers with 5KV isolation have 5V CMOS). Then the margin is tight. I think I must use level shifter as you stated that I must avoid TTL for future.
