AVR Freaks

Ok looks like it does count down but does not load back to 8.

asm volatile(
		"	clr %0					\n"//clear counter
		"	clr r17					\n"//clear temp
		"	ldi r18,8				\n"//set counter
		"	ld  r17, Z 				\n"//load Z to r17

		"	rjmp waitlow	\n"
"nextElement:\n"
SET_DBG
CLR_DBG
		"	ldi r18,8				\n"//set counter
		"	st  Z+, r17 			\n"//load r17 to z and go to next element in array
		"	ld  r17, Z 				\n"//load Z to r17
"waitlow:\n"
		" ldi r16, 0xff				\n"	

"waitlowl:\n"//start bit.
		"	inc r16					\n"//time out counter
		"	brmi exit			\n"// > 255, long enough for near 50us or so.
		"	sbic %2, 5				\n"//check if low,then skip
		"	rjmp waitlowl			\n"//wait while low.
		"	inc %0					\n"//count this bit.
		"	nop						\n"//move 1us in to place.
		"	nop						\n"
		"	nop						\n"
		"	nop						\n"
		"	nop						\n"
		"	nop						\n"
		"	nop						\n"
		"	nop						\n"
		"	nop						\n"
		"	nop						\n"
		"	nop						\n"
		"	nop						\n"

							// check at this time for bit state
		"	sbic %2, 5				\n"//if state was low skip
		"	sec   			  	    \n"//set Carry flag if true
		"	rol r17 				\n"//Rol flag on to r17

		"	ldi r16, 0xff				\n"
"waithigh:\n"
//find the next rising edge to sync
		"	inc r16					\n"
		"	brmi exit				\n" // > 255, long enough for near 50us or so.
		"	sbis %2, 5				\n" //check for set then skip
		"	rjmp waithigh			\n"	//go back not ready
		"	dec	r18					\n" //bit counter
		"	brne nextElement		\n"
		"	rjmp waitlow		\n" //next element in array

"exit:	\n"
		: 	"=&r" (count)						// %0
		: 	"z" ((unsigned char volatile *)nBuffer),		// %1
			"I" (_SFR_IO_ADDR(GCN64_DATA_PIN)),	// %2
			"I" (_SFR_IO_ADDR(PORTB))			// %3
		: 	"r16","r17","r18"
	);

I know my debug is not the best. The ICE is on the way.

The first 8 bits do count down but once it jumps to next element, its like the LDI didnt set r18 to 8? Please mind the code, I'm not finished, work my  way thru it.

or

dec  r18

   brne someplaceElse, happens ever bit.

   brne someplace, only after 8

like posted above.

Quite glad I initiated this thread, found all of this very helpful..

Ok so the code all works now, here is what I have. There seems to be one little issue left that I'm %99 sure is in my code.

After the code is complete I always have a bit that is on that should not be on.  Second byte, bit 5

After the first ST instruction something is setting my 5th bit. 

		asm volatile(
		"	clr %0					\n"//clear counter
		"	clr r17					\n"//clear temp
		"	ldi r18,8				\n"//set counter
		"	ld  r17, Z 				\n"//load Z to r17
		"	rjmp nextBit	\n"
"nextByte:\n"
		"	ldi r18,8				\n"//set counter back to 8
		"	st  Z+, r17 			\n"//load r17 to z and go to next element in array
		"	ld  r17, Z 				\n"//load Z to r17
"nextBit:\n"
		" 	ldi r16, 0xff			\n"
"waitlow:\n"//start bit.
		"	dec r16					\n" //time out counter
		"	breq exit				\n" //exit when we hi zero( carry flag and dec are equal. )
//find the next falling edge to sync
		"	sbic %2, 5				\n" //check if low,then skip
		"	rjmp waitlow			\n" //wait while low.
		"	nop						\n" //move 1us in to place.
		"	nop						\n"
		"	nop						\n"
		"	nop						\n"
		"	nop						\n"
		"	nop						\n"
		"	nop						\n"
		"	nop						\n"
		"	nop						\n"
		"	nop						\n"
		"	nop						\n"
	//	"	nop						\n"
		//"	nop						\n"
		//"	nop						\n"
		//"	nop						\n"
		CLR_DBG
		SET_DBG

// check at this time for bit state
		"	sbic %2, 5				\n" //if state was low skip
		"	sec   			  	    \n" //set Carry flag if true
		"	rol r17 				\n" //Rol flag on to r17
		"	inc %0					\n" //count bit.
		"	ldi r16, 0xff			\n"
"waithigh:\n"
//find the next rising edge to sync
		"	dec r16					\n"
		"	breq exit				\n" // exit when we hi zero( carry flag and dec are equal. )
		"	nop						\n"
		"	nop						\n"
		"	sbis %2, 5				\n" //check for set
		"	rjmp waithigh			\n"	//go back not ready
        "   dec    r18              \n" //bit counter
        "   brne nextBit      		\n" //If carry flag and dec are  not equal.
		"	rjmp nextByte			\n" //If carry flag and dec are equal. 

"exit:	\n"
		: 	"=&r" (count)						// %0
		: 	"z" ((unsigned char volatile *)nBuffer),		// %1
			"I" (_SFR_IO_ADDR(GCN64_DATA_PIN)),	// %2
			"I" (_SFR_IO_ADDR(PORTB))			// %3
		: 	"r16","r17","r18"
	);