For joeymorin: AVR8 timers, fast PWM, COMxy = 01

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Hey, joey--Are you still on your hot streak?

 

In https://www.avrfreaks.net/comment... we were discussing CTC and FOC and natural compare matches.

 

Then in https://www.avrfreaks.net/comment... a somewhat related question about output compare made me notice the 01 setting combination of the COM bits in Fast PWM.

 

I never really paid attention to that combination.  Apparently, it turns Fast PWM into CTC, and only affects the A output (???).  Do you think this is just the way the chip logic came out for an otherwise unused/meaningless combination?

 

It does serve to offset the action which in CTC mode would be at TOP, to an arbitrary point in the timer period.  Is that the use?

 

From 16-bit Timer1, Mega164PA family datasheet:

...

 

For 8-bit Timer0 in the same family, it is even more confusing to me:

...

 

 

That would then be modes 4-7, right?  Modes 4 and 6 are thunks.  As modes 5 and 7 have OCR0A as TOP, doesn't the combination then degenerate to CTC?

 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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theusch wrote:
Hey, joey--Are you still on your hot streak?
I'm sure its end is imminent... hey, how did this become about me?! :)

 

theusch wrote:
I never really paid attention to that combination.  Apparently, it turns Fast PWM into CTC, and only affects the A output (???).  Do you think this is just the way the chip logic came out for an otherwise unused/meaningless combination?
Perhaps, but I'd say it's a way of having control over TOP with OCRnA to fine-tune the period of the timer and remaining PWM outputs, while retaining the ability to use the output 'consumed' by the use of that OCRnA register.  That output is limited to a 50% square wave at twice the timer's configured period, but that might still be useful for some apps, perhaps ones which require a clock synchronised with the PWM outputs.

 

Although in the OP's case (your 2nd link) there are modes 8,10, and 14 which use the ICRn register for TOP, freeing the use of all compare outputs for PWM, I would point out that not all timers have input capture and an ICRn register.  For the simpler 8-bit timers (like TIMER0), using compare output mode 1 for OCnA lets you:

  • tune the timer's period
  • use OCnB as a PWM output
  • generate a square wave clock on the OCnA output, synchronised to the PWM channel

 

I personally have never made use of this mode.

 

 

theusch wrote:
It does serve to offset the action which in CTC mode would be at TOP, to an arbitrary point in the timer period.  Is that the use?
For modes where TOP is not derived from OCnA, yes.  An extension of the use case I outline above?

 

theusch wrote:
For 8-bit Timer0 in the same family, it is even more confusing to me:

 

 

That would then be modes 4-7, right?  Modes 4 and 6 are thunks.  As modes 5 and 7 have OCR0A as TOP, doesn't the combination then degenerate to CTC?

Actually, it's referring to modes 3 and 7 only.  Fast PWM.  For mode 3, WGMn2 is 0, and for mode 7 it is 1.  In mode 7, yes you are correct it 'degenerates' to CTC, but only for OCnA.  OCnB can be configured for proper PWM.  For mode 3, the output toggle can be positioned at any offset w.r.t the pulses generated on the OCnB output.

 

Remember also that since these uses are PWM, the output compare register are buffered, which has some impact on the way in which you may manage them in software.

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

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joeymorin wrote:
freeing the use of all compare outputs for PWM, ...

 

But no, OC1B is disconnected, right?

 

WGMn3:0 = 14 or 15: Toggle OC1A on Compare
Match, OC1B disconnected (normal port operation).
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.

 

joeymorin wrote:
Although in the OP's case (your 2nd link) there are modes 8,10, and 14 which use the ICRn register for TOP, freeing the use of all compare outputs for PWM,

From above, only mode 14 applies.  So I still don't see any possible use of that COM combination.

 

Hmmm--the only way to get a "soft PWM" of some sort where all you want is the events to trigger on, but not drive the port pin(s) directly?

 

Never mind.  Have a good holiday season.  My place is already turning into a ghost town.  And record high temperature today...

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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theusch wrote:
But no, OC1B is disconnected, right?
When configuring COMnB[1:0] = 0b01, yes.  Configuring COMnA[1:0] has no effect on OCnB.

 

WGMn3:0 = 14 or 15: Toggle OC1A on Compare
Match, OC1B disconnected (normal port operation).
For all other WGM1 settings, normal port operation,
OC1A/OC1B disconnected.

I'm not sure which datasheet/revision you grabbed that from.  In ATmega640/1280/1281/2560/2561 (2549P–AVR–10/2012) from the Techlib DVD:

 

 

This is saying that when configuring the COMnA[1:0] bits, compare mode 1 will toggle OCnA.  When configuring COMnB[1:0], compare mode 1 leave OCnB disconnected.  Similarly for OCnC.

 

Basically, only OCnA can be made to toggle on a compare match in a PWM mode, but there is no 'linkage' between the settings which control the individual compare match outputs.

 

 

 

theusch wrote:
joeymorin wrote:

Although in the OP's case (your 2nd link) there are modes 8,10, and 14 which use the ICRn register for TOP, freeing the use of all compare outputs for PWM,

From above, only mode 14 applies.

Quite right.  There does seem to be some non-orthogonality in the manner in which the capabilities are spread out among the different modes.

 

Whereas it is only the OCnA output which can be configured for toggling in a PWM mode, the Fast PWM and Phase (and Frequency) Correct PWM modes don't have the same capabilities.  For Fast PWM, toggling on OCnA is supported both for mode 14 where TOP = ICRn, and for mode 15 where TOP = OCRnA.  However for Phase (and Frequency) Correct PWM modes, only modes 9 and 11 support OCnA toggling, both of which derive TOP from OCRnA.  Modes 8 and 10 which derive TOP from ICRn do not support OCnA toggling.

 

Thinking on it, I'd say the nature of a dual-slope PWM would make toggling a redundant if you think about it.  With dual-slope, 'normal' (and 'inverted') compare output mode will clear (or set) when up-counting, and set (or clear) when down-counting.  With a toggle mode, it would amount to exactly the same thing, effectively 'normal' or 'inverting' depending on the initial state of the compare match unit.  If the logic of the toggle mode is anything like what I proposed in my last post (synchronised clock), then a dua-slope toggle mode could not produce that (at 50% duty, anyway).  Only when OCRnA = TOP would a 50% duty square wave be produced by toggling.

 

theuscy wrote:
Hmmm--the only way to get a "soft PWM" of some sort where all you want is the events to trigger on, but not drive the port pin(s) directly?

 

Never mind.  Have a good holiday season.  My place is already turning into a ghost town.  And record high temperature today...

Burning hot here, too.  No snow for my nephew and his toboggan addiction.  He's terribly disappointed.  No snow for my father and his snowmobile addiction.  He's terribly disappointed ;-)

 

Got lots to do before the big day and not much time to do it, so I'll likely as not be absent from these parts for a few days...

 

Happy holidays!

 

 

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

Last Edited: Wed. Dec 23, 2015 - 11:35 PM
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joeymorin wrote:
I'm not sure which datasheet/revision you grabbed that from.
theusch wrote:
From 16-bit Timer1, Mega164PA family datasheet: ...

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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Here's a screenshot of that table:

 

 

Note how this table is 'generic' in that it applies to both the COMnA[1:0] >>and<< the COMnB[1:0] bits.  The details for each are broken out in the each 'Description' field.  The implication is >>not<< that selecting mode 1 for COMnA[1:0] will also force mode 1 for COMnB[1:0].  Rather, the implication is that the technical writers are lazy ;-)

 

Note how the corresponding tables for TIMER2 are separated:

 

 

 

Note also the typo in table 17-3 where OC0A should be OC2A :(

 

I've not been able to suss out why in most (all?) datasheets the TIMER2 tables are split by the A and B outputs, whereas for the other timers the A and B outputs are combined into one table.  The only semantic difference which I can spot is that for TIMER2, mode 1 on output B is 'reserved' instead of 'disconnected'.

 

I have a sneaking suspicion that a single technical writer has been responsible for all of the TIMER2 datasheet sections across all devices, and he/she simply chose a different style.

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]