AVR Freaks

That's an issue of endianness (in print, not in the device).  When I write a 16-bit word, I write it with the MSB on the left, and the LSB on the right.

 

The AVR hardware, however, is little-endian, so a 16-bit word in byte-oriented addressing is stored with the 8 LSB before the 8 MSB.  Since Intel hex files are byte-oriented, the 16-bit instruction word appears to you to have the high byte and the low byte swapped.

 

As an example, if I take an AVR hex file I have lying around, the first line looks like this:

:100000000C9463000C948B000C948B000C948B006C

... with the first 32-bits of the payload highlighted.

 

If I disassemble that hex file with avr-objdump -Dzmavr:

Disassembly of section .sec1:

00000000 <.sec1>:
       0:       0c 94 63 00     jmp     0xc6    ;  0xc6

Note how the order is presented the same way.  However, since this is little endian, the actual two 16-bit instruction words are written as 940c0063, written with MSB on the left.

 

This is a bit pattern of:

1001 0100 0000 1100 0000 0000 0110 0011

1001 010k kkkk 110k kkkk kkkk kkkk kkkk

 

So you see a match with the Instruction set manual.

 

The constant is a bit complicated.  22 bits is enough to address 4M words.  Devices with 128K of flash (or less) need only address 64K words (or less), and use only 16 of those bits.  They are the 16 bits in the 2nd 16-bit instruction word.  In our example above, that's 0x0063.  When taken as a byte-address that points to 0x00C6, which avr-objdump confirms above.

 

See:

http://web.csulb.edu/~hill/ee346/Lectures/16%20AVR%20Instruction%20Encoding.pdf

 

EDIT:  typos