After several days of debuging with my SPI driver for CC2420, I finally found the bug, it's a issue with CS pin timing.
CC2420's datasheet said the CS pin need to be low for at least 25ns after the last negetive edge of SCLK. And in my driver code, I used the hardware support for controlling the CS pin and didn't set any delay for DLYBCT, so the result is that CS pin is pulled up at the same time of SCLK negetive edge.
Now the problem is that if I set DLYBCT as 1, it would introduce 33 MCK delay between any transfers. This is too much for me!
I'm thinking of using software to control CS pin, but is this really the only option?