I'm designing a PCB that will have multiple SOIC8 ATtiny85s, while developing they will of course need to he flashed numerous times but even when finished there will be upgrades, bug fixes etc.
So my question is, how can I implement the ISP for all these chips?
My current circuit looks like this (for 2 chips, this will be replicated 8 times making 16 processors in total).
- 1: The application requires all the SPI signals to be in parallel.
- 2: There are 16 PGM signals (PGM1-16) running to a header, they can be connected with a flying lead to the RST of the programmer.
- 3: The normal RESET function has to be maintained, hense the BAT75 so a system reset gets all chips but a programming reset only affects the chip being programmed.
- 4: SS is handled in software, in theory all chips NOT being programmed will hold MISO in tri-state and ignore the activity on the other lines.
- 5: If however I get a rogue chip that won't release it's MISO line I will be in trouble, to handle this I might allow each chip's VCC to be disconnected or just flash it to force it to behave. Assuming I can identify the culprit that is.
- 6: SPI lines will be buffered so the programmer doesn't have too much loading.
- 7: There's almost NO way to add components, the board is chocka block, but for a creative idea I might be able to rearrange a few things, I haven't run traces yet.
- 8: I know I should have pullups on RST, I'll have to rely on the internal one.
Any faults in this, or better ideas?