I'm using the ATtiny416. POR kicks in somewhere between 1.4 and 1.8 volts as long as Vdd is rising slowly enough. But I've got some FETs on the board that can turn on at 1.0 volt. I've got pull downs on the FET gates, but if the I/O pins of the ATtiny416 were to be driven high while Vdd is rising from 0 to 1.4 volts even for a few microseconds, it could short out my H-bridge. So my question is, "Are the I/O pins undefined while Vdd is rising from 0 to POR?" I was using a Motorola DSP56F805 years ago, and some of the I/O pins would be driven high briefly during power up, and every once in awhile that would smoke an H-bridge. At Texas Instruments, we had a few 7400 series logic gates which had been analyzed and proven to remain in a known state during power up. We would use those gates for power-up related functions. I've asked MicroChip technical support this question, but my technical support person doesn't seem to understand the question. She keeps telling me that the I/O pins remain tri-stated until POR is released.
Joined: Mon. Mar 16, 2015
Posts: 38 View posts