Interrupt over SPI bus

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I have an application where I'd like the SPI slave to send an interrupt to the master. The hardware is fixed, and there is no way to add a separate pin for the interrupt.

So what I wonder is if there is a conventional way of sending an interrupt from SPI slave to SPI master using only the four SPI pins.

I have started work on defining such a transport protocol, but before I dive into the code I'd like to know if something like this exists as a standard.

If it doesn't I'll be happy to share my thoughts and code.

Cheers,
Børge

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Just out of interest

1) are there any other connections between the chips

2) what type of AVR is the master - IOW is it a "modern" one where most IO (including the SPI lines when not used) are PCINTs or not?

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The only other connection is the reset signal, and it's hard to repurpose it.

The MCU is an atmega32. But the slave is an FPGA where I can make the HW do pretty much anything in parallel.

My general idea was to use MISO as the interrupt line. It becomes the AVR's pull-up input line while any slave can pull it low. On my board there is room for a series resistor for MISO. But to be allowed to pull MISO low, the slaves must monitor MOSI and SCK. Only when MOSI is '1' and when SCK has been static for some time, may the slave pull MISO low.

So the MCU will clear MOSI a bit before clearing any CSN signals. Between bytes in an SPI transfer it will also clear MOSI. And after CSN goes high again the MCU will wait for some time before once again setting MOSI.

Detecting MOSI=='0' or an any edge on SCK resets an internal timer in the slave. Only after this timer times out may the slave use MISO to signal an interrupt.

The various slaves do this in a wired-AND fashion so that every slave must be polled to find the one which signalled the interrupt.

With sufficient delays and PCINTs this should also be feasible in an MCU. What's important for me is that the FPGA can signal an interrupt while all other SPI devices are left blissfully unaware of the state of things. Since MOSI goes low before any CSN goes low, and since it stays low for some time after CSN has gone high again, the slave which wishes to signal an interrupt has to Hi-Z MISO before any SPI device is activated.

Børge