I have an application (Tiny25) that uses INT0 rising/falling edge interrupts. During the INT0 ISR, a pin is multisampled, so the ISR requires 30usec. The application also sends out bufferred, bit-banged RS-232 data during a Timer0 CTC ISR.
I'd like to re-enable global interrupts during the INT0 ISR multisample loop. The simplest method to prevent INT0 reenterantcy would be to clear the INT0 bit in GIMSK register. However, I wonder if there is a better way using the INT0F flag.
The datasheet states the INT0F flag is set when an INT0 interrupt occurs and "is cleared when the interrupt routine is executed". At what point is the INT0F cleared: start of ISR, end of ISR (RETI instruction), or at some undefined time during ISR processing?
My second question is whether the INT0F being set prevents another INT0 interrupt from occuring.
Overall, I wonder if the INT0F remains set throughout the entire INT0 ISR (and is cleared by the RETI instruction) and if that the set INT0F prevents reenterant INT0 interrupts. Then, I could simply reenable global interrupts to handle the Timer0 rs-232 output while not worrying about reenterant INT0 interrupts.
Thanks for your time considering these questions.