Interrupt flags and reenterantcy

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I have an application (Tiny25) that uses INT0 rising/falling edge interrupts. During the INT0 ISR, a pin is multisampled, so the ISR requires 30usec. The application also sends out bufferred, bit-banged RS-232 data during a Timer0 CTC ISR.

I'd like to re-enable global interrupts during the INT0 ISR multisample loop. The simplest method to prevent INT0 reenterantcy would be to clear the INT0 bit in GIMSK register. However, I wonder if there is a better way using the INT0F flag.

The datasheet states the INT0F flag is set when an INT0 interrupt occurs and "is cleared when the interrupt routine is executed". At what point is the INT0F cleared: start of ISR, end of ISR (RETI instruction), or at some undefined time during ISR processing?

My second question is whether the INT0F being set prevents another INT0 interrupt from occuring.

Overall, I wonder if the INT0F remains set throughout the entire INT0 ISR (and is cleared by the RETI instruction) and if that the set INT0F prevents reenterant INT0 interrupts. Then, I could simply reenable global interrupts to handle the Timer0 rs-232 output while not worrying about reenterant INT0 interrupts.

Thanks for your time considering these questions.

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For a quick and dirty test, temporarily "borrow" an output pin from elsewhere and have the ISR put the INT0F bit on it. Then you'll be able to see if the bit is cleared or set when the ISR runs.

Chuck Baird

"I wish I were dumber so I could be more certain about my opinions. It looks fun." -- Scott Adams

http://www.cbaird.org

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Short answer: that bit will be cleared when you ENTER the ISR. [That allows the next event to be "queued" while servicing this one, instead of "blocking" the next event till [say] the ISR is completed.]

I assume you are debouncing the INT0 (though a few us is shorter than any typical button or switch bounce). If you want to let timer0 fire, then I'd disable the interrupt as you mentioned. Then clear the bit and re-enable the interrupt before leaving the ISR.

Be careful with the stack effects of nested ISRs. Especially with a brand of compiler that shall not be named, a lot of stuff is stacked upon entry to the ISR.

Lee

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

Last Edited: Mon. Oct 8, 2007 - 06:52 PM
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That's a reasonable idea, Chuck. Or, I could use debugWIRE to examine the state. While a casual examination would give me an idea of the behavior, I'm reluctant to rely on undocumented behavior. Thus, I wonder if Atmel has a document that details the operation of the interrupt flags.

And, of course, the second half of the question, "does the INT0F flag prevent INT0 reenterancy" can be tested in a similiar fashion. But, again, I'd strongly prefer to rely on specifications rather than observed behavior. In general, if it's not specified, I consider any behavior to be possible.

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ATtiny45 data sheet page 12 wrote:
There are basically two types of interrupts. The first type is triggered by an event that sets the Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vector in order to execute the interrupt handling routine, and hardware clears the corresponding Interrupt Flag.
This section is correctly read in the context of how the AVR responds to an interrupt. Just like Lee said:
theusch wrote:
Short answer: that bit will be cleared when you ENTER the ISR.
Taken in context the documentation is quite clear about this. So, you do not need to worry about this being undefined or displaying random behavior.

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Mike, thanks for the clarification.

Lee, I'm afraid I read your answer too quickly and glanced over your "Short", but complete, answer.

I now fully understand what I need to do.

Thank you very much, gentlemen!