Trying to get my head round interrupt driven EEPROM writing on a Mega16.
In the interrupt driven approach, there is no need to poll the EEWE status bit to verify whether the previous write cycle has completed. The EEPROM Ready Interrupt is constantly triggered when the EEWE status bit is cleared. It is however still necessary to poll the SPMEN status bit if Self-Programming is used, to make sure a Self-Programming operation is not currently active. The primary advantage of an interrupt driven approach is that dedicated hardware can request processing power when needed; this decreases the processor load.
The confusion is around
The EEPROM Ready Interrupt is constantly triggered when the EEWE status bit is cleared.
Constantly triggerred? Does it really meant that - surely not? Triggered once I could understand...
AVR104 only has C code examples for writing a SRAM buffer to EEPROM - does anyone have any example/reference code in ASM before I have to sort out my confusion and then code it from scratch?