Hi,
Device ATxmega192A3
Compiler Imagecraft
Debugger AS4
I tryed also AS6 and i see the same problem.
I prefere to use Imagecraft.
I am checking the Non-Volatile-Memory, NVM, controller mechanism's to update application flash.
My code is loaded in the boot-section of the Mc.
BOOTRST Flag is set, interrupts vectors are moved to Bootsection. Power supply, 3,7V, is stable.
I run from an external 3,6864Mhz cristal, but i see the same phenomena when running from the internal oscillator.
First, i fill up the Temporary buffer with sequential data 0001 -> 00FF. It is not executable code but it does not mather, it is just to check the flash update mechanism.
In an assembler procedure the SPM instruction is given, where after i enter a loop to check the NVM.STATUS bits7 and Bit6.While filling Temporary buffer these bits never come high. So here i don't have the problem.
Second, i clear the flash page that i want to write.
The SPM instruction is given in another assembler procedure, where after i jump to the same procedure to check the NVM.Status Bits. In this case Bit7 and Bit6 become high. This means that NVM Controller is busy clearing the given flash page.
Third, we give the command to write the written temporary buffer into the given Flash page.
Again we check the status bits, also here Bit7 and Bit6 are high.
In the cases where Bit7 and Bit6 are high i notice that i jump out of the while loop in the __WAIT_NVM_FREE__: assembler procedure
_fill_temp_buffer::
XCALL __WAIT_NVM_FREE__
movw r30, r16 ;move adress to z pointer (R31=ZH R30=ZL)
movw r0, r18 ;move data to reg 0 and 1
sts NVM_Cmd,r24
SPM ;Store program memory
XCALL __WAIT_NVM_FREE__
RET
;-----------------------------------------
_write_page::
XCALL __WAIT_NVM_FREE__
movw r30, r16 ;move address to z pointer (R31 = ZH, R30 = ZL)
sts NVM_Cmd,r18
LDI R24,0x9D ;Load immediate
OUT 0x34,R24 ;Out to I/O location
SPM ;perform pagewrite
XCALL __WAIT_NVM_FREE__
RET
;-----------------------------------------
__WAIT_NVM_FREE__:
LDS R27,NVM_Status; ; load NVM_Status Byte to R27
ANDI R27,0xC0 ; Logical AND with immediate
BRNE __WAIT_NVM_FREE__ ; check NVM_STATUS flag
RET
;-----------------------------------------
When i Step true the Code i never have the problem.
When stepping the NVM operation is already completed.
I only see the problem when running at processor speed.
I place a breakpoint on the RETURN instruction. in the __WAIT_NVM_FREE__ procedure.
What is see is that R27 = 0xC0 and the zero flag is NOT set. Why do i hit the return instruction when the zero flag is NOT set !!!!!!!!!!!!!
There is a screen shot attached, myzip.zip, where you can see this situation.
Notice that in the failure case The H and the C flags are Set. In cases when i don't see the problem, it is not failing every time, the Half Carry and the Carry flags are NOT set.~
I tryed also the following.
I nop out the proceudre __WAIT_NVM_FREE__ in assembler.
In C i define tree 1000 bytes buffers in RAM.
We initialise the buffers on 0xFF.
After every NVM action Fill_Temp_Buffer, Erase_Flash_PAge and Write_Flash_PAge, i read out NVM_STATUS byte a 1000 Times. This is done in
procedure Check_NVM_STATUS
Also here i start reading C0, NVM is busy, and suddenly i jump out of the 1000 Bytes write Loop.
In this case the L_i value has a extreem high value 4053 Decimal !!!!!
The main c file is attached.
Conclusion.
Strange instruction behaviour when NVM actions are running. If i NOP out the SPM instruction, i don´t see any of these sympthoms. So it has to do with the fact that SPM is executing.
Has someone seen such behaviour?
Or what do you think about this?
