I am designing a very minimal synchronous ATmega-to-CPLD interface with a shared common clock, CLK (CKOUT fuse programmed), and data bus. The ATmega and CPLD are directly connected to each other. Since the ATmega latches input data on falling CLK, the CPLD updates data output on rising CLK. The design presumption is that the data will be stable when the ATmega latches it, since the CPLD and ATmega are running off the same clock.
It would be helpful to know the ATmega GPIO timing specifications with respect to CLK to be able to determine the fastest allowable clock frequency. I have been unable to find detailed timing specs in the datasheet, app notes, forums, or internet search.
Are there timing specifications for ATmega GPIO and external clock drive, CLKO with respect to internal CLK (let's say an ATmega328 for example)? In particular, are there specifications for:
a. input (synchronizer latch) setup/hold time
b. output delay (OUT instruction)
c. external clock drive, CLKO, delay