Input Synchronizer Latch Setup/Hold Timing

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I am designing a very minimal synchronous ATmega-to-CPLD interface with a shared common clock, CLK (CKOUT fuse programmed), and data bus. The ATmega and CPLD are directly connected to each other. Since the ATmega latches input data on falling CLK, the CPLD updates data output on rising CLK. The design presumption is that the data will be stable when the ATmega latches it, since the CPLD and ATmega are running off the same clock.

 

It would be helpful to know the ATmega GPIO timing specifications with respect to CLK to be able to determine the fastest allowable clock frequency. I have been unable to find detailed timing specs in the datasheet, app notes, forums, or internet search.

 

Are there timing specifications for ATmega GPIO and external clock drive, CLKO with respect to internal CLK (let's say an ATmega328 for example)?  In particular, are there specifications for:

a. input (synchronizer latch) setup/hold time

b. output delay (OUT instruction)

c.  external clock drive, CLKO, delay

 

Thank you,

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I don't recall seeing such information in the datasheets. I believe most ATmega can be overclocked to 25MHz so I'm guessing the sum of delays inside the chip is less than 40ns (for VDD = 5V and normal operating temperatures).

Last Edited: Sun. Dec 15, 2019 - 11:22 PM
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looks like setup & hold times could be 67ns  ..do a search for txldx & tdvxh  in data sheets  ...this might have some bearing on what is going on.. 

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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Thanks for the ideas.

 

Judging from the input synchronizer schematic and timing diagrams in the datasheet, I am thinking that the GPIO input latch setup time is at most half a clock cycle (25 ns @20 MHz), since that is how long it is transparent.
 

I measured the setup time for an ATmega328 (32M1-A package marked "ATMEL M328P U-CN") on an Arduino Nano at 5V as best I could, and got approximately 22.5 ns. Hold time was 0 or negative.