IDE/HDD "Getting started guide"

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I just started whit a new project where I want to connect a HDD to my Mega16l wich is currently sitting firmly in my STK500.
I have hacked a 40 pin IDE cable to connect the HDD to the STK500.
It's wired like this:

PORTA <--> DD07:DD00

PORTB <--> DD15:DD08

PORTC:
PIN7 <- IRQ
PIN6 -> /Write strobe
PIN5 -> /Read strobe
PIN4 -> /C1
PIN3 -> /C0
PIN2 -> A2
PIN1 -> A1
PIN0 -> A0

PORTD: (Wired to the leds and buttons on the STK500)
PIN7 <- SW0
PIN6 <- SW1
PIN5 -> LED0
PIN4 -> LED1

PORTE/AUX
RST -> /Reset
GND -- GND
VCC -- DMARQ
VCC -- DMACK

I have downloaded several IDE/ATA documents and also some sourcecode for different AVR based MP3 players, but I'm unable to extract even the most basic functions from it.

I tried to make a program that upon pressing a button, would read the status register and test the BSY flag, and if that was cleared, turn on LED0 and test the RDY flag, and if that was cleared, turn on LED1 and go on to put the HDD in sleep mode.
Short story: I couldn't make it work.
If I enabled pull-upps on the data busses, I never got a cleared BSY flag, and whit no pull-upps, I got the flags, but the command didn't work.

I know that the reset system is working, cause when I connected a CD-ROM and opened the tray (while everything was powered on), pushing the reset switch on the STK500 would close the tray again.
Anything beyond that, I haven't been able to work.

If someone could be so kind as to explain (in great detail) how I could make the HDD go into sleep mode (Turn off spindle motor for acoustic verification of desired operation) or any other basic and verifiable operation, I would be a very happy camper!
-DX-

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http://www.atmel.com/dyn/resources/prod_documents/ATA_HardDrive.pdf

I came across this a long while ago. It explains the basics of taking to HDDs. Read this several times and understand it. Then armed with your new knowledge Google for the bits you don't understand or find someones project and take it appart until you understand the code.

http://www.circuitcellar.com/library/print/0103/eady150/index.htm

Good luck! I shall be starting my player soon too. 1.8" HDD over UDMA66. 100Mbs Ethernet. USB2 480Mbs. 2.2" Colour screen and QWheel scrolling. So a fair amount to learn there. Google is your friend. Trick is to narrow down your search to very specific points. There's no point in searching for a complete project that does everything you want - break it down in to chunks and teach yourself.

Tim

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The Procyon avrlib by Pascal Stang (not to be confused with avr-libc, the runtime lib for the AVR-GCC compiler) contains code for IDE interfacing as well as a (read only) implementation for FAT16/32. A walkthrough of this code might help You gain insight. Go here: http://hubbard.engr.scu.edu/embedded/avr/avrlib/

From the documentation:

Quote:

This code is based in part on work done by Jesper Hansen for his excellent YAMPP MP3 player project.

So You might also find good stuff here: yampp.com

As of January 15, 2018, Site fix-up work has begun! Now do your part and report any bugs or deficiencies here

No guarantees, but if we don't report problems they won't get much of  a chance to be fixed! Details/discussions at link given just above.

 

"Some questions have no answers."[C Baird] "There comes a point where the spoon-feeding has to stop and the independent thinking has to start." [C Lawson] "There are always ways to disagree, without being disagreeable."[E Weddington] "Words represent concepts. Use the wrong words, communicate the wrong concept." [J Morin] "Persistence only goes so far if you set yourself up for failure." [Kartman]

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I've spent some more time to try to get this to work...
Currently, I have PORTA wired like this:http://www.circuitcellar.com/library/print/0103/eady150/l1.htm.

I have tried using the data patterns listed to get the status register.
Basically, I set up the pattern on PORTA, and pulled the read strobe low, waited a bit (nop) and then reda D15:D00 into r17:r16 through PORTB:PORTC (Pullups enabled), then set the read strobe to high, and feeding r17:r16 out to the PC through the UART.

Even if the HDD appears to be working just fine in the PC, the status register (in the HDD) returns 01h (wich is to indicate something is wrong).
Reading the error register (Atleast I think that's what I'm doing), I get 01h again.
This seems to indicate that I'm doing something wrong.
I have alot of pins going nowhere. Maybe they are causing some trouble??

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All input pins should be tied to a know state otherwise they can indeed cause trouble.

Are you able to read anything other that 01h? Can you return the manufacturers information for example, or reset the drive? If not then it's possibly a wiring fault.

Tim

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From reaing some more, I found that this other guy had tied the DMA lines to Vcc, and so did I.
This made me able to read the status register properly.
I have made some code that constantly polls this egister and put it out on the UART if it has changed since the last polling.
During powerup (of the HDD) the register flickers, but then settles on alternating between 52h and 50h, wich I think is apropriae behaviour, as the alternating bit would be the index-marker bit.
Whit this, I'll try to do something more complicated... Like sending commands to the drive.

Maybe I should write an article on "Beginners guide to interfacing whit a Harddrive", cause what I have found myself, is either way too complex, or lightheartedly skip by the basics alltogheter...

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Searching for "mp3 ata (or ide) avr", finds a ton (almost) of source code and schematics.

Rick

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I know.. But where I am at the moment... Those are rather complicated to decipher.
The fact that I know little or nothing about C doesn't help much either...
Just now, I managed to make the drive spin down by the push of a button, and then spin back up by the push of another button.
I'm struggeling to get a grasp on the most basic principles of the IDE/ATA systems.

To read the ECh (Identify drive) results... Should I just send the command, and wait for the DRQ bit to go active, and then read the data register repeatedly to get all of the words in the 256x16bit buffer, or do I have to adress each word in the buffer... These are the things that I'm gritting my teeth over right now :)

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This is the moment of learning. If you could see a 1 page c program that had a little hot key menu and each key called a subroutine, you would have the whole hd thing compartmentalized down to where you could understand each function. I remember doing a floppy program a couple decades ago and you need select, motor on/off, seek a track, read sector, write sector, format track subroutines.

Imagecraft compiler user

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Progress!!!
Right now, I have just "mastered" sending the "Identify drive" command, and reading back the information provided.
And for my former question... pulsing the read strobe would read 16 "fresh" bits from the HDD on each pulse, until all the 256 words are transfered.

I think I'm starting to get a grip on this subject.
Still haven't got any data from the physical HDD media, but that's next on the list.

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Home Run!!
Alright!
At last, I can read from and write to the HDD.
This has been a tricky one, but I managed to extract the information I neede from various sources on the net.
The problem, really, was that there was too much information out there, but nothing aimed for "beginners" like me.
I'm not sure if anyone else would benefit from a tutorial aiming at beginners, but I'm ready to write one if you guys think it would be useful.

My routines are not very optimized, but that's not the point.
I know how to wire the HDD to the AVR and I know how to talk to it, and make it do what I want it to do :)

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Quote:

I'm not sure if anyone else would benefit from a tutorial aiming at beginners, but I'm ready to write one if you guys think it would be useful.

That would be great! It sounds like you're making some real progress here. I'm sure this info would be very helpful to others.

Mike H.

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I 'm so freakin' tired right now, but here's what I have put togheter so far:
http://www.dukerx.no-ip.com/ide.htm

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Hi

this is very nice guilde "how to start with ide" http://www.pjrc.com/tech/8051/id....

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DukerX,

While I'm sure many appreciate the huge work you've done in creating your guide, I'm sorry to say that it's loaded with errors.
As you refer to the ATA docs in several places, why didn't you read them yourself and made a correct drawing with the proper signal directions of the 40-pin connnector ?
The way you describe the signals may be cool for a 13 year old, but stuff like "dude, yeah, this is a ground pin, yeah" isn't exactly a good way of trying to explain the function of the signals.
Also, tying DMARQ to VCC is NOT a good idea as it's an output from the drive !
/IDE_CS0 and /IDE_CS1 does not in any way address (1F0-1F7 and 3F6-3F7). Those are the addresses of a the ATA controller in a PC. But you have no explanation of what they REALLY do, or what the A0-A3 address pins does.

You complained yourself that you couldn't understand other code and documentation you found on the net. I can guarantee you than even less people will understand yours. It's VERY tied to your exact configuration of pins and the order of these. You have hardcoded bitpatterns in the code.

Don't take this personal, but that guide sucks. It will just confuse people even more, I'm afraid.
But you seem to have the energy, time and dedication to write such a guide, so I suggest you spend some months playing with the ATA interface and learn how it really works, THEN write the guide.

Peter Fasses guide at Pauls PJRC page is now very old and also suffers from many of the same issues as yours, it's way too locked to a certain processor and wiring.

I'm sure a PROPER guide would be VERY popular, so keep up the good job, but make sure you make it right.

/Jesper
http://www.yampp.com
The quick black AVR jumped over the lazy PIC.
What boots up, must come down.

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jesper wrote:

Peter Fasses guide at Pauls PJRC page is now very old and also suffers from many of the same issues as yours, it's way too locked to a certain processor and wiring.

Thats right but its still the best "Getting started guide" I have found. Only ATA spec. is better, but its a too long. And IMO PIO mode is enough fast for ATMELs so I cant see reason why use ULTRA DMA 166))). And every PATA HDD is back compatible with old ATAs.

BTW: In the guilde is written

Quote:

RDY bit. indicates that the disk has finished its
power-up. Wait for this bit to be active before doing
anything (execpt reset) with the disk. I once ignored
this bit and was rewarded with a completely unusable
disk.
. Can be possible to destroy HDD just by sending it bad command?

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Iguaner wrote:
jesper wrote:

Peter Fasses guide at Pauls PJRC page is now very old and also suffers from many of the same issues as yours, it's way too locked to a certain processor and wiring.

Thats right but its still the best "Getting started guide" I have found. Only ATA spec. is better, but its a too long. And IMO PIO mode is enough fast for ATMELs so I cant see reason why use ULTRA DMA 166))). And every PATA HDD is back compatible with old ATAs.


Who said anything about using DMA ? PIO mode is obviously the way to go with AVR's, but you need to get the connections right and not burn out the drivers in the disk.

Quote:

BTW: In the guilde is written
Quote:

RDY bit. indicates that the disk has finished its
power-up. Wait for this bit to be active before doing
anything (execpt reset) with the disk. I once ignored
this bit and was rewarded with a completely unusable
disk.
. Can be possible to destroy HDD just by sending it bad command?

No, ofcourse not. But you can overwrite data when writing if not looking at this bit properly. Ignoring RDY did not destroy the disk. Something else did.

I just read some more in the guide and the description of and use of RDY and DRQ bits are incorrect. You should wait for DRQ before reading/writing data, not just RDY.
DRQ is NOT an indicator for less than 512 bytes as described. There's ALWAYS 512 bytes in a disk block.
It's all described in the ATA specs. Perhaps not very clearly, but it's there. Read it all.
Also, get the ATA3 (rev7) guide instead of the ATAPI4 version. It's less bloated and easier to read and understand.

/Jesper
http://www.yampp.com
The quick black AVR jumped over the lazy PIC.
What boots up, must come down.

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Hi

I have Two question:
1) If you send disk command to read sector with LBA 0, but not read all 512 bytes, but only 200 bytes and than send read command for sector with LBA 1. What will you read than from HDD? Bytes 201 and 202 from sec 0 or bytes 0 and 1 form sec 1?
2) Is 8 bite communation mandatory or options?

BTW: In FAT spec is written

Quote:

Many FAT documents mistakenly say that this 0xAA55 signature occupies the “last 2 bytes
of the boot sector”. This statement is correct if — and only if — BPB_BytsPerSec is 512. If
BPB_BytsPerSec is greater than 512, the offsets of these signature bytes do not change (although it is
perfectly OK for the last two bytes at the end of the boot sector to also contain this signature).

But have someone seen sector with size != 512bytes? Even CF cards has 512 bytes sectors.

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I know there are many "holes" in my guide, and also something dead wrong :P
I wrote it early in the morning, before going to bed. I was too tired to work on the actual project, so I just put togheter that piece of (mis)information.
It's just a rough draft. The reason I posted it here was to get feedback on it.. Not to be a "real" document yet.
Maybe I should have stated that in the post.

Anyways... I'll go through it and correct the errors and silly remarks soon...

The reason I wrote it the way I did, was so that people could get "up and running" whitout having to read and understand the entire 300 page ATA document.
Regarding the DRQ bit and 512 bytes... True.. It's never going to be LESS then 512 bytes in the buffer, but in many cases there is more...

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Quote:
1) If you send disk command to read sector with LBA 0, but not read all 512 bytes, but only 200 bytes and than send read command for sector with LBA 1. What will you read than from HDD? Bytes 201 and 202 from sec 0 or bytes 0 and 1 form sec 1?

You will read bytes 0 and 1 from sector 1. It's perfectly legal to terminate a read in the middle of a block. Not a good idea to do that on writes though !
Quote:
2) Is 8 bite communation mandatory or options?
It's outdated and you will be VERY VERY lucky to find a hard disk that would support that today.

/Jesper
http://www.yampp.com
The quick black AVR jumped over the lazy PIC.
What boots up, must come down.

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Quote:
The reason I wrote it the way I did, was so that people could get "up and running" whitout having to read and understand the entire 300 page ATA document.
Yes, but you see, the problem is that after reading your guide (errors aside), they're not any wiser as you do not describe anything about registers, bits or addressing. They can blindly copy it and perhaps get a disk to work, but they will be left totally in the dark.
If they make just the tiniest little mistake, nothing will work and there's NO way for them to refer to the guide and get help.

The sad thing about all this ATA stuff is, that if you really wants to know what's going on, you HAVE to READ _AND_ UNDERSTAND those 300 pages. And that's just the beginning, then comes a few hundred pages of FAT specs e.t.c.

Quote:
Regarding the DRQ bit and 512 bytes... True.. It's never going to be LESS then 512 bytes in the buffer, but in many cases there is more...
Not on a standard hard disk.
While it may, on some disks be possible to use a larger block size, that disk would be totally unusable if connected to a PC.
On CDs and DVDs, the block size is 2048 bytes, but that's quite different in many other ways.

/Jesper
http://www.yampp.com
The quick black AVR jumped over the lazy PIC.
What boots up, must come down.

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I have built an IDE board which is used to talk to CDROMs to play music, haven't tried to talk to an HDD yet. One thing I found is that an 8 MHz Mega8515 or Mega 8535 can be too fast for the IDE buss (or was it the CDROM too slow?? ) so I had to put quite a few nops in the read and write registes routines. Of course having an 8255 chip between the micro and the IDE buss may slow things down a bit so it may be ok. There is a lot of info around including Jesper's website. I started off by looking at other people's code for different processors (including some dreaded C programs :-) ) and of course trying to underastand the 7 different ATAPI standard etc. Once you start to get things happening then it should be a lot more easy sailing., ie get your basic ATA commands working reliably.

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

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I started over on that tutorial. It's not finished yet, but if you would like to comment on it, I would aprechiate the feedback.
It's located at dukerx.no-ip.com/ide-guide/

It's slightly less "Hitchikers guide to the galaxy"-ish then my first attempt, as I had just finished reading that book when I wrote it.

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Excellent, excellent, excellent!

I wish more people would put forth the effort to produce such great stuff. Fantastic!

I hope you put forth the effort to create more like it.

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I have added some more to the IDE tutorial.
Let me know what you think about it.

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Excellent Job!

How about doing more on different topics, especially the easy stuff for newbies like Setting-Up Timer or UART, etc.

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Much better, DukerX.
But you stil have some errors in how you handle the DRQ bit.
It should always be checked before reading/writing data. RDY and BSY id for other status.

/Jesper
http://www.yampp.com
The quick black AVR jumped over the lazy PIC.
What boots up, must come down.

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jesper wrote:
And that's just the beginning, then comes a few hundred pages of FAT specs e.t.c.

Where did you get so long FAT spec? I have one from Microsoft and it has only 32 pages. Cna you send me link or tip where to search?

BTW: The name of pin 37 is CS0 and 38 CS1.

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Iguaner wrote:
BTW: The name of pin 37 is CS0 and 38 CS1.

0.o

Don't go there...
I've seen both names being used, but the CSnFX are the ones in the specs.

@Jesper
I haven't found any conditions that would cause the DRQ flag to be cleared other then the data transfer being completed, or a new command being executed.
Granted the data buffer is always 256 words... Shouldn't it be suficcient to check the DRQ flag after transfering a 256 word block?

It's not a big issue, as the DRQ checking routine could easily be implemented in the same routine that is used for the BSY checking. Just curious.