i2s - bidirectional

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I2S is generaly known to be single directional and 3-wire, however in some designs I see a 4th. line, where last line is dedicated for upload. I cant find any spec for a 4wire I2s, can someone in here??

Regards
Vidar (Z)

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"The fool wonders, the wise man asks"

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I2S Audio usually has a data line, a bit clock line, a word clock line, and master clock line (usually something like 256xbitclock).

Or unless it is data out from some like DSP chip.

Or do you even mean I2S Audio?

- Jani

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I2S/PCM is the one standard I reffere to (not I2C), with normally I2S_CLK (bit clock), I2S_WS (word select or left right or word clock), and I2S_SD (serial data, from master to slave), the master clock are not so common but it is used to some ext., however, an extra data line I have never seen, atleast not for bidirectional behaviour.

One example where you will find a I2S bus with the extra data line for upload is the LM4935 from National. There are however dificult to find a complete description for the I2S standard describing all possebilities.

Anyone?

Regards
Vidar (Z)

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"The fool wonders, the wise man asks"

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The chip you describe is a codec, it has both a DAC and an ADC. That is why it has both SD input and SD output.

You give it PCM data on SDI line, it outputs analog audio on speaker output. You give it analog audio to its ADC input, it outputs PCM data to you on SDO line.

This is really nothing, my current work project involves 8 channel PCM audio on 4 SD lines, converting it to TDM and feeding it to DSP, and I hate it :)

- Jani

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Google is not my friend, it has never been and will never be.. Alltheweb, however, is.

But if reading the NXP spech (former Philips) for the I2S bus, it is only discussing the most common 3-wire solution. It does not discuss 4-wire bidirectional busses or master clk lines. These are extensions to the I2S standard (afaik, atleast, correct me if I am wrong) which is not to easy to find documentations for.

However, from Jepael's last response I guess I can handle both data lines in the same way, where I am the master in any data flow direction...

Note: Youst for the record. The example chip given is not the one I am working with, only given as a refference. I am studying a hw platform I am aboute to get involved in and I had youst not seen any bidir I2S yet.

Regards
Vidar (Z)

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"The fool wonders, the wise man asks"

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Well I would not call it bidirectional. Or an extension. You can think of that like separate DAC and ADC chips, both glued together. And some chips need the master clock to process the stuff, so it's not necessarily just for clocking the bitclock and wordselect lines, but can be used for that too.

It's just that somebody has to be the master who generates some of the signals.

In case of the DAC, you send it data, but the bit clock and frame sync can be generated by you for the DAC or the DAC for you, and that is usually based on the master clock.

In case of the ADC, it sends you data, regardless of who generates bit clock and frame sync.

Master clock is usually used by ADCs and DACs to provide sigma-delta or delta-sigma type conversions and oversampling. Or they can use the master clock to derive word select and bit clock for you.

- Jani