I'd like to know if the following I2C schem is possible :
- One I2C Master sends one I2C command of several data bytes (Write command) on the broadcast address, but instead of sending STOP condition, it sends START again and begin a reading sequence with one of the 3 slaves
- 3 SLAVES (3x Atmega328p) receive this first write command in interrupt driven mode (TWI_Vect IRQ), and then 1 of the 3 the read command.
Is it possible that 1 of the 3 slaves engage clock stretching (SCL forced at LOW) by software after any of the ACK condition (more specificaly : for example the last ACK of the write sequence)?
If it's possible, then what will happen :
The master will send the new START to begin read sequence and block ? Or will the master wait releasing of the SCL line before sending the new START ?
How would you do that in software ? I thought that after sending an ACK, I can just disable interrupts by clearing TWIE. Will it be enough to force SCL low until I set TWIE again to continue reading sequence ?
Thanks in advance for your answers