I am working on a SAM G55 processor, using I2C to communicate with an external flash chip.
The flash device has a write cycle during which it does not acknowledge. It describes a procedure for "acknowledge polling" to know when it is ready for the next command.
It is described as follows:
This involves the master sending a Start condition, followed by the control byte for a Write command (R/W = 0). If the device is still busy with the write cycle, then no ACK will be returned. If no ACK is returned, the Start bit and control byte must be resent. If the cycle is complete, then the device will return the ACK and the master can then proceed with the next Read or Write command.
I have not yet found a way to do this. If I try to send just a Start condition and a control word, with no data, nothing is transmitted on the bus. In the datasheet for the processor, it says as follows:
After the master initiates a START condition when writing into the TWI Transmit Holding Register (TWI_THR), it
sends a 7-bit slave address, configured in the Master Mode register (DADR in TWI_MMR), to notify the slave
device. The bit following the slave address indicates the transfer direction, 0 in this case (MREAD = 0 in
This sounds to me as though the chip only will send the START condition and the control word when a byte is queued for transmission, which is exactly what I do not want to do, according to the datasheet for the flash device.
Is there some way to overcome this impasse, or is there something I am misunderstanding?
(When I try to use _i2c_m_sync_transfer with a zero length message, nothing at all is transmitted on the bus, supporting my understanding of the datasheet.)