Hi, Im looking at code that is directly setting the bits for SCL and SDA, with appropriate delays. Aiming to get code for a eeprom write read from an M8.
Well there are "tutorials", "specifications" (especially for the one chip Im working; 24LC16), "all you need to know" etc.
However, all more or less contain exactly the same text with minor variations and same figures. None of which I can find
to describe the sequence for receiving the ack after a byte write, when multiple bytes are written.
I.e. Im currently into trying to get the sequence for write to eep right. (possibly I have an eye problem, or dont read well enough)
(There can also be different take in same document; where the SDA (from the acking part) goes high IN the SCL flank or in the following SCL low (doubious) )
Well, would appreciate if someone has a pointer to good description, or can explain the order, and where the next byte starts after the ack reception. (like some german text
... :) )