How to use a watchdog in a multi-interrupt setting

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I want to make my software safer by using a watchdog
(a short interruption for restart is no problem).
In total it is a sort of digital software receiver running
functions in real time with different sample rates.

The problem is, that there are some independently
running functions and I think I want to make
sure that all functions operate properly.

The structure is as follows:

A fast timer1 interrupt running at about 10k interrupts per second.
Every 8 timer1-interrupt this routine fills one A-value into a FIFO.

The main-program is an infinite loop.
Always if A-values are ready in the FIFO, the main loop
triggers a function that fetches the A-values from the FIFO
and computes a new B-value using these values.

Then there is a timer2 interrupt that triggers a function
1000 times per second. This function takes the actual B-value
and computes a C-value and putputs bits on a port..

If I would reset the watchdog in the interrupt-routines
and one timer interrupt would be disabled due to a
malfunction, then the other interrupt would still
reset the watchdog and so the watchdog in this
simple way makes no sense.

The problem for me is: How can test that all the different
functions work properly.

In short: How to use a watchdog in a multi-interrupt setting?

Any suggestions welcome!

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First why do you have two timer interrupts, can't the timer2 ISR just be some code timer1 run every 1/10 time? (or is this a xmega?)

But never mind.
Try to define a sanity test for each program part (and set/clear a flag), and how they sync to each other, (like main should not take longer than x timer 1 ISR's etc.).
And if you meet all then kick the watchdog and clear flags, in the main program. (Perhaps in your setup the timer1 ISR are the main program! )

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What you describe is effectively the perennial problem of where you put the watchdog kicker(s) in an OS environment. Do you put it at the core of the OS scheduling to simply ensure that the entire system does not lock up or do you rely on all the tasks sprinkling them liberally so no task can get "stuck". It's actually a very tricky design decision.

It might be best to try and gauge "what's most likely to lock up?" then save the protection for that alone.

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I seem to remember that The Usch has a system he uses for this sort of thing. No doubt he'll be along soon and point you at it, but if not, I think he sets a flag in each ISR, and then clears the watchdog based on the AND of all such flags. I guess the flags are all cleared when the watchdog is reset.

Four legs good, two legs bad, three legs stable.

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Here's what I'd suggest (sounds like it might be similar to John's suggestion):
Set up a watchdog interrupt to check run flags for each independent thread. For speed of checking, I'd use one of the GPIO registers. So bit0 could be for timer0, bit1 could be timer1, and bit3 could be your main loop. Each thread clear's its watchdog bit on each iteration. When the watchdog ISR runs, it checks the GIPIO register. If it is zero, it sets it to 7, and exits the ISR. If it is non-zero, one of the threads didn't reset it's watchdog bit, so the AVR should reset. To trigger the rest, clear WDIE, so the next time the watchdog times out the AVR will reset instead of running the watchdog ISR.

I have no special talents.  I am only passionately curious. - Albert Einstein

 

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Quote:

I seem to remember that The Usch has a system he uses for this sort of thing. No doubt he'll be along soon and point you at it, but if not, I think he sets a flag in each ISR, and then clears the watchdog based on the AND of all such flags. I guess the flags are all cleared when the watchdog is reset.


Exactly. One mention:
https://www.avrfreaks.net/index.p...

Be sure to read the whole thread for other views, especially danni's a few posts down.

Another interesting discussion I uncovered when searching for the above, but a hair different topic: "Watchdog--good or evil". ;)
https://www.avrfreaks.net/index.p...

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I've never met a pig I didn't like, as long as you have some salt and pepper.