How is SPI supposed to work?

Go To Last Post
29 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I want to communicate data from one or more ATTiny's to an ATMEGA using SPI.

The ATMEGA is the master and gives separate enables (SS?) to each ATTiny.

The master also is the source of clock.

 

First problem is I can't find any data on how SPI is really supposed to work.

I have read the ATTiny datasheet and it only gives an example of bit-bashing

with a software loop that loops for every bit. I even seriously doubt this works

in the slave as there is no way to synchronize the bit timing with the clock

coming from the master.

 

However, this surely can't be the way SPI is supposed to work?

 

How I hope it is supposed to work is that you load a byte into the slave's output

register (some documents call that SPDR but there is no such register name in the Tiny!)

which automatically starts (??) the byte being shifted out to the master by the master-supplied clock (??)

 

But wait - the Master started it's clock already. How is the slave's software supposed to know that?

And if and when it does, how long does software have to load the first byte into the "SPDR" register?

One bit time or less? Geez!  Does that mean no other interrupts can be enabled  when the SPI

port is in use if they would delay things by as little as one bit period? Geez!

 

Now assuming there is a food answer to the above questions, when the byte has finished output

( 16 clock edges have been detected) and you get a clock-edge-counter-overflow interrupt,

how long do you have to get the next byte into the "SPDR" register? One bit period again?

That would be 1uS in our case. (The clock from the master is still coming relentlessly.)

 Again that means no other interrupt can be enabled when SPI is in

use until the clock from the master stops or SS is taken down.

That would be a pretty awful limitation.

 

I must be missing something.

It seems like SPI output should be double-buffered like a UART would

be so that you have a whole byte-time to get the next byte in place,

but I not seeing that on the hardware diagram or in the description in

the ATTiny datasheet.

 

Please can somebody who understands interrupt-driven SPI elucidate?

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I even seriously doubt this works

in the slave as there is no way to synchronize the bit timing with the clock

coming from the master.

When you are the slave, you would "bit-bash" by reading the data bit value  on MOSI when the clock SCLK makes its transition.  (that would be rising or falling depending on your mode)  At that time, you slave would also present the next bit value on MISO for the master to read.

 

First problem is I can't find any data on how SPI is really supposed to work.

Must be your first rodeo.  The Mega datasheets aren't all that bad in the description and diagrams.  Or start somewhere more generic such as Wikipedia.  In short, it is a full-duplex shift register.

 

I have read the ATTiny datasheet and it only gives an example of bit-bashing

with a software loop that loops for every bit.

Now I need to detour on why you are putting yourself through this agony in the first place.  What is the advantage to having multiple Tinys in your design?  Surely it must be more expensive and take more board space and introduce synchronization delays.  And development is more complex, as you are finding out.

 

Answer/Suggestion 1:  Don't distribute the design unless it is really warranted

Answer/Suggestion 2:  Examine the choice of SPI for communication, vs. e.g. USART

Answer/Suggestion 3:  Pick slaves that have a real SPI peripheral subsystem

Answer/Suggestion 4:  Look at the app notes for USI.  AVR309 pops up first but there might be others.

 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

When you walk thru your design with your peers, they might aks these questions: How many slaves are there? How far away are they? How many bytes per sec do they collect and send back? Why not just hang em all on a reliable old RS485 multidrop that will run at 1MHz?

Imagecraft compiler user

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

"When you are the slave, you would "bit-bash" by reading the data bit value  on MOSI when the clock SCLK makes its transition."

 

Yes I could set up a pin change interrupt from the clock line, and when the right polarity flank is detected, read the MOSI line.

 

But that is just pin-wise digital I/O.   SPI would be doing zilch for me in that case.

I have done serial I/O on the MEGA exactly like that, using 3 non-SPI pins

 

The only point of having hardware called SPI would be to relieve the software of that burden, as a UART would.

 

Can someone make my day and show me that SPI in slave mode can do that, or is SPI truly useless?

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

The task is to AtoD convert 16 analog signals simultaneously at the rate of 480 samples per second each. For about $2 and no board area.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

"Pick slaves that have a real SPI peripheral subsystem"

 

Can you suggest one that has at least 8 AtoD inputs?

 

 

I should add to my previous description of the task that, as well as

AtoD converting 8 channels simultaneously at 480 samples per second each,

the TINY does 8-point FFTs on every block of 8 samples, and sends the results to the

ATMEGA. The fixed-point FFT code is very fast on the Tiny as the only multiply is

by the same 8-bit constant over and over which I do with a look-up table,

(since the TINY doesn't have hardware multiply)

and we are very glad that we have relieved the MEGA of that job, as it it pretty

busy with other stuff.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

The task is to AtoD convert 16 analog signals simultaneously at the rate of 480 samples per second each. For about $2 and no board area.

Your Mega costs more than that.  So re-specify.  Or are you trolling?

 

If all you need to do is convert those samples, then use a chip with 16 A/D channels.

 

Can someone make my day and show me that SPI in slave mode can do that, or is SPI truly useless?

You didn't read my whole response, did you?  I might have a typo in the last line; I think it is AVR319...

 

 

Speaking of "re-specifying", most microcontrollers will not get "simultaneously" samples of 16 channels.  But round-robin conversions of 16 channels at 480 samples/second is about 8ksps which is reachable with an AVR8.

 

So, at 2 bytes of info each sample, what are you going to do with the 16KB of info gleaned every second?

 

At a guess, on the Mega side, the overhead to garner these 8K samples each second with SPI will be more than simple ADC-complete ISR handling.  (That is maybe 10us every 200us so 5% of CPU.)

 

Now, if it were me, I'd use an Xmega with twin ADC and set up a DMA/event system to scan the channels continually in rotation.  As far as I know, that would take no CPU load.  The app code could look at the buffered result values whenever it cared to.  Which Xmega series would depend on the rest of the app.

 

Tinys are about a buck in quantity.  ATxmega8E5 is about a buck in quantity, and has 16 ADC channels and a true SPI peripheral.  So I've already saved you a buck.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

ATtiny828 is about a buck in quantity, and has 28 A/D channels and a true SPI peripheral. 

 

Attiny441 family is about a buck in quantity, and has 12 A/D channels and a true SPI peripheral.

 

One of our favourite Tinys around here is the '1634.  Not expensive with a lot of memory and peripherals as Tinys go.  There I'd suggest streaming the date via USART.  But it only has 12 A/D channels.

 

 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Answer/Suggestion 1:  Don't distribute the design unless it is really warranted

Getting back to this:  As an AVR8 person we apply the Mega640 when we need a lot of "stuff".  And it has 16 ADC channels.

 

It costs about $7 in the quantities where my previous mentions cost a buck.  Would be a wash if your Mega now is $5 plus two Tinys at a buck each.

 

 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

The question was really "how does SPI work". The truth: nothing more than an externally clocked shift register with an active-low select/enable pin. In a slave, the data input pin is called MOSI (Master Out, Slave In) and the data output at the far end of the register is called MISO (Master In, Slave Out). Look at a 74C164, and you will know almost all of how slave SPI works. The master does most of the heavy lifting (which is not much).

 

QUOTE:  I even seriously doubt this works in the slave as there is no way to synchronize the bit timing with the clock coming from the master.

 

Yes, it IS how it works. In the case of a microcontroller, this is often dedicated static logic, not clocked by the internal MCU clock. And, there is something that counts clocks so that the slave knows when its register data has been shifted out. Bit banged slave has a severe limit on the maximum clock rate from the master.

 

The slave IS responsible for loading the right data at the right time into the register. But, that is about it.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

Last Edited: Thu. Oct 8, 2015 - 10:04 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Has the OP's "specification (with my emphasis) been overlooked?

convert 16 analog signals simultaneously

 

Ross McKenzie ValuSoft Melbourne Australia

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

An avr can read the a/d at  about 20000 reads a sec. So thats 16 channels 1200 times a sec. Sounds do-able on one avr. A much simpler program than 16 spi slaves. But the spi does in fact work. The idea is when you store a byte in the master transmit, the clock shakes 8 times and the byte shifts out. If the clock also goes to the slave, he will shift in his byte while the master is shifting out his. So you can get full duplex at a megabyte per sec.

Imagecraft compiler user

Last Edited: Fri. Oct 9, 2015 - 01:25 AM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

First line of his first post reads:

I want to communicate data from one or more ATTiny's to an ATMEGA using SPI.

The ATMEGA is the master and gives separate enables (SS?) to each ATTiny.

 

Then, there is some about ADCs. Not sure what he wants.

 

Jim 

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

ka7ehk wrote:
First line of his first post reads:

I want to communicate data from one or more ATTiny's to an ATMEGA using SPI.

The ATMEGA is the master and gives separate enables (SS?) to each ATTiny.

 

Then, there is some about ADCs. Not sure what he wants.

OP's first post is quite clear:

He wants to know how to do SPI so that he can transmit data from multiple slaves to a single master.

 

Why are you unsure?

 

OP also described slave code that suggests he picked slaves without hardware SPI.

Not a good design choice, but does not really change the question.

It does change the answer: Get slaves with hardware SPI.

 

A multi-processor system might have been a bad design choice,

but that does not render OP's first post any less clear.

 

Using AVRs might have been a bad choice in itself.

Perhaps a stand-alone 16-channel ADC and a fast enough processor would have been better.

This might be a case of OP using what he thinks he knows.

 

What AVR has the largest number of simultaneous ADC channels?

Iluvatar is the better part of Valar.

Last Edited: Fri. Oct 9, 2015 - 06:00 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

What AVR has the largest number of simultaneous ADC channels?

;)  Be more clear in your specification.  I.e., is AVR32 an "AVR"?

 

I did some poking for my answers above, but I think for an AVR8 none have more than one ADC.  And Xmega models typically have two, right?  But with interleaved I guess you could say they have four, with a one clock cycle delay?

 

 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

No Mega or Tiny AVRs have simultaneous ADC operation. 

 

There MAY be some such capability in XMega devices.

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

theusch wrote:

What AVR has the largest number of simultaneous ADC channels?

;)  Be more clear in your specification.  I.e., is AVR32 an "AVR"?

An emoticon does not turn something nasty into something funny.

What helped was the information provided later in the post.

Quote:
I did some poking for my answers above, but I think for an AVR8 none have more than one ADC.  And Xmega models typically have two, right?  But with interleaved I guess you could say they have four, with a one clock cycle delay?

Iluvatar is the better part of Valar.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

If we take 'simultaneously' in the literal sense, the answer may be very much different then if it is taken to mean 'fast round-robin'.
480x16 = 7860 sps. That is well within the capability of an AVR8. At 8 MHz and /64 ADC prescaler, you can achieve 9615 sps at 10 bits. If you only need 8 bits, a /8 prescaler will get you 76923 sps. At that rate, 16 round-robin samples will all be sampled within 200 us, compare to a 2083 us sample period (480 sps).

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

An emoticon does not turn something nasty into something funny.

???  Sheesh, bad day at the office?  We'd just gone back-and-forth  about "specification" and "simultaneous".  As you asked about "AVR", isn't it valid to ask (with a wink) whether you would include AVR32 in your universe selection?

 

[I'd speculate that the app doesn't need true simultaneous conversion on many channels.  [[The mention of the Tiny(s) to do the job supports this.]]  But something like an Xmega with twin ADC "channels" and interleaved operation and fast converter could do continuous conversions with only some few microseconds max between signal samples.]

 

I fear the return to the bit-bashed SPI stuff has driven away OP.  In the end, the exact same situation would exist if one substitutes "UART" for "SPI".  Bit-banged UART is certainly possible.  But would one want to construct an AVR8 app with more-or-less continuous transmission/reception at a high bit rate?  I'd say no.

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

skeeve wrote:
theusch wrote:
Quote:

        What AVR has the largest number of simultaneous ADC channels?

    ;)  Be more clear in your specification.  I.e., is AVR32 an "AVR"?
An emoticon does not turn something nasty into something funny.
What helped was the information provided later in the post.
Quote:
I did some poking for my answers above, but I think for an AVR8 none have more than one ADC.  And Xmega models typically have two, right?  But with interleaved I guess you could say they have four, with a one clock cycle delay?
theusch wrote:
Quote:
    An emoticon does not turn something nasty into something funny.

???  Sheesh, bad day at the office?  We'd just gone back-and-forth  about "specification" and "simultaneous".  As you asked about "AVR", isn't it valid to ask (with a wink) whether you would include AVR32 in your universe selection?

Were the question valid, a wink would be neither necessary or useful.

We both had the same context available.
What helped was the information provided later in the post.
You did not end with the snark.

 

Actually you might be better able to answer the question than I:
Other than the obvious, I know little about AVR32s.
OP might be sticking with AVRs because of learning curve issues.
The AVR8 to AVR32 learning curve is something you might know better than I.

Iluvatar is the better part of Valar.

Last Edited: Fri. Oct 9, 2015 - 10:22 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Simultaneous conversion is used for arrival time comparison.... microphones, hydrophones. Like radar only slower time of flight?

 

 

Imagecraft compiler user

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 1

PaulWDent wrote:
First problem is I can't find any data on how SPI is really supposed to work.

Please can somebody who understands interrupt-driven SPI elucidate?

 

It's actually simple. Everything is under control of the master. 

 

So if you are the master: You assert the desired slave select. Then you load the outgoing SPI data register. The hardware takes over, and generates the SPI clock, and shifts out your going data on MOSI while simultaneously shifting in the slave data on MISO. When the operation is complete, you get an interrupt, or you can simply spin on whatever shift-done indicator the hardware provides. When the shift is done, you can read the incoming SPI receive data register to get what the slave sent.

 

If you're only writing to the slave, you can ignore what shifts in.

 

If you're only reading from the slave, you still have to load something in the outgoing data register for the shift operation to start.

 

That's it.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Thank you all for all these comments.

3 years later and a lot of hit and miss programming I now know a bit more about SPI and got it working fine.

If documentation was complete, concise, error free and unambiguous we would not need this site, would we !!

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Paul SPI has been around for more than 30 years, not much more than a shift register, if you don't know how it is supposed to work it's not Atmel's fault but yours for not studying enough at college or uni.

 

The SPI docs are perfectly fine and I got it working pretty much first go about 16 years ago and in assembler even. Had Motorola SPI working even a lot longer.

 

And if you keep on reviving old threads we may need to start deleting some of your posts.

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 1

John -

 

Never leaned one iota about SPI at uni. Doubt that "modern" classes say any more.

 

That said, SPI is not difficult to learn - it is probably the very simplest of all of the "simple serial interfaces" (UART, I2C, SPI).

 

Jim

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 1

Every AVR datasheet (for devices with SPI) has that picture showing the sending and receiving shift registers. Surely that picture alone tells you almost the entire story?

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

PaulWDent wrote:
a lot of hit and miss programming

That'll be the problem right there!

Top Tips:

  1. How to properly post source code - see: https://www.avrfreaks.net/comment... - also how to properly include images/pictures
  2. "Garbage" characters on a serial terminal are (almost?) invariably due to wrong baud rate - see: https://learn.sparkfun.com/tutorials/serial-communication
  3. Wrong baud rate is usually due to not running at the speed you thought; check by blinking a LED to see if you get the speed you expected
  4. Difference between a crystal, and a crystal oscillatorhttps://www.avrfreaks.net/comment...
  5. When your question is resolved, mark the solution: https://www.avrfreaks.net/comment...
  6. Beginner's "Getting Started" tips: https://www.avrfreaks.net/comment...
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Never leaned one iota about SPI at uni.

Didn't you? surprise the uni I went to UHK (aka university of hard knocks) had courses on everything and had to learn very fast before the Internet was around, why I even had to read books to which I'm allergic to now.

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Oh, yes,  UKH taught me a lot. Brick and mortar (or concrete and glass) uni did not, in this regard, anyway. Learned lots of other stuff, though :=)

 

 

Jim Wagner Oregon Research Electronics, Consulting Div. Tangent, OR, USA http://www.orelectronics.net