I want to communicate data from one or more ATTiny's to an ATMEGA using SPI.
The ATMEGA is the master and gives separate enables (SS?) to each ATTiny.
The master also is the source of clock.
First problem is I can't find any data on how SPI is really supposed to work.
I have read the ATTiny datasheet and it only gives an example of bit-bashing
with a software loop that loops for every bit. I even seriously doubt this works
in the slave as there is no way to synchronize the bit timing with the clock
coming from the master.
However, this surely can't be the way SPI is supposed to work?
How I hope it is supposed to work is that you load a byte into the slave's output
register (some documents call that SPDR but there is no such register name in the Tiny!)
which automatically starts (??) the byte being shifted out to the master by the master-supplied clock (??)
But wait - the Master started it's clock already. How is the slave's software supposed to know that?
And if and when it does, how long does software have to load the first byte into the "SPDR" register?
One bit time or less? Geez! Does that mean no other interrupts can be enabled when the SPI
port is in use if they would delay things by as little as one bit period? Geez!
Now assuming there is a food answer to the above questions, when the byte has finished output
( 16 clock edges have been detected) and you get a clock-edge-counter-overflow interrupt,
how long do you have to get the next byte into the "SPDR" register? One bit period again?
That would be 1uS in our case. (The clock from the master is still coming relentlessly.)
Again that means no other interrupt can be enabled when SPI is in
use until the clock from the master stops or SS is taken down.
That would be a pretty awful limitation.
I must be missing something.
It seems like SPI output should be double-buffered like a UART would
be so that you have a whole byte-time to get the next byte in place,
but I not seeing that on the hardware diagram or in the description in
the ATTiny datasheet.
Please can somebody who understands interrupt-driven SPI elucidate?