In mega64 data sheet and CAN128 data sheet, in free running or auto tigger modes it says:
"The actual sample and hold takes place 1.5 ADC clock cycles after the start of a normal conversion"
On the timing diagram, sample & hold is shown as a single event.
But I need to know when the sample takes place and when the hold takes place. Perhaps in the data sheet they mean that the sample starts at 0 and the hold takes place after 1.5 ADC clock cylcles. Does anybody know?