How to filter out a power-on spike?

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I have an ATTiny85 design that I power from a 24VDC wall wart.  My circuit has an LDO generating 5VDC from the 24VDC (there are no other active components on the 5V rail so there's not a lot of power dissipated in the LDO).  The Tiny controls a MOSFET which controls a 24VDC solenoid.  When I plug the cable from the wall wart into my board I get a spike on the 5V rail that sometimes exceeds 8V (though just for a few microseconds).  Enough of this finds its way to the IO pins to trigger the gate on the MOSFET, triggering the solenoid when I don't want it to be triggered.  I've tried a range of caps on the 5V rail and the specific IO line in question, from .01 uf up to .1 uf, but without consistently reliable results.  Any suggestions for how to filter out this spike?  Thanks.

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What LDO are you using and what caps are present in your basic design?

 

Jim

 

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You could put a Zener on the 5v rail to clamp the spike.

 

But a schematic would speak volumes.  Can you post one?

 

JIm

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Do you have a pulldown resistor on the port pin/gate? Also, does your code set the PORT value before setting the DDR value?

 

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Thanks for the comments.  Attached is a schematic.  No pulldown on the port pin.  DDR is set before writing to the port.  I like the zener idea, but all comments welcome.  Btw, R3 is used to drop the voltage to about 14V to reduce power dissipation through the regulator (better to dissipate some through the resistor).

Attachment(s): 

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Dumb question...possible that you have the regulator in backwards?

 

JIm

I would rather attempt something great and fail, than attempt nothing and succeed - Fortune Cookie

 

"The critical shortage here is not stuff, but time." - Johan Ekdahl

 

"Step N is required before you can do step N+1!" - ka7ehk

 

"If you want a career with a known path - become an undertaker. Dead people don't sue!" - Kartman

"Why is there a "Highway to Hell" and only a "Stairway to Heaven"? A prediction of the expected traffic load?"  - Lee "theusch"

 

Speak sweetly. It makes your words easier to digest when at a later date you have to eat them ;-)  - Source Unknown

Please Read: Code-of-Conduct

Atmel Studio6.2/AS7, DipTrace, Quartus, MPLAB, RSLogix user

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The values for CAP2 (0.33 ufd) and CAP3 (0.1 ufd) are below my comfort level., I'd prefer at least 5 ufd for each and a separate 0.1 ufd bypass at the processor.

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Confirmed it's wired correctly.  Wouldn't be getting 5V out if it weren't.

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The cap values are per the datasheet.  I did skimp on the CPU bypass thinking the .1 uf output cap is right next to the CPU so it could do double duty (heh heh).  This is a very space-constrained design so I was looking for space savings anyplace I could get them.  I realize there should be one in principle, but I don't get the sense that's what's causing this particular problem.  Not having much luck with a zener, btw.  Doesn't seem to be having any effect (and I DO have the black line end connected to VCC through a 100 ohm resistor).

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Per Kartman's suggestion, a 1K pulldown seems to solve the problem.  I'm still seeing some major spikes on that gate (> 16V), but I can't get it to trigger spuriously (maybe they're too fast?).  I'll play around with it some more, but hopefully that solves the problem.  Thanks for all the suggestions.  I'd still like to know why the zener didn't work.  Maybe I'll do some tests on a breadboard to refresh my understanding of their operation.

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I would seriously increase the capacitance at the INPUT of the regulator. 

 

Is there can't be a spike at the input of the regulator because of the 1K resistor and the 0.33uf cap. That makes a time constant of 0.33ms. That ought to give you a smooth input rise as the wall supply comes on, but making CAP2 = 1us would give an input time constant of 1ms and that still ought to be fast enough.  

 

Thinking about it, this HAS to be an issue with the regulator. Input turn on is likely smooth with no overshoot. If this is true, then any output spike HAS to be the regulator. Unless there is some sneak path through the switching FET. Try it with the FET disconnected. and verify whether or not the spike is still there. Thinking about it more, there is a LOT of capacitance between the FET drain and gate. Maybe the high dV/dT from the supply turning on is coupling through that device capacitance and pulling the micro supply higher than it should be. Check for spike when the FET is disconnected from its load (or, remove the load) so that there is NO 24V DC at the drain.

 

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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i'd suggest the spike is due to the measurement technique. The pulldown I'd suggest a 10k rather than 1K - 500uA vs 5mA.

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"I'd still like to know why the zener didn't work."
The zener in an "... (and I DO have the black line end connected to VCC through a 100 ohm resistor)" arrangement cannot clip the VCC transients.
The Absolute Maximum Rating for the ATtiny85 is 6 V, so I'd be using a 5.1V or 5.6V (my preference) zener directly across the VCC-GND rails.

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A zener is not the best choice for transient protection. A TVS diode would be a better choice.
My suspicion is the spike gets coupled into the 'scope but what is seen is not representative of what is actually happening in the circuit.

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Have you a diode across the solenoid? How good is your earth on the PCB? Is the solenoid powered from the same 24v PSU?  

 

David

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Also, I notice PB3 has no input protection - and it is next to the solenoid connection. I don't think this will work well.