How does an SPI slave know it's received new data?

Go To Last Post
10 posts / 0 new
Author
Message
#1
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

I'm thinking of using SPI in a project, specifically in daisy-chain mode where I might have 10 slaves and one master (all ATMegas of a variety TBD).  How does a slave know when it has new valid data to read?  I can see how data clocks in from the master and simultaneously clocks out from the slave, but I can't see how the slave can tell the clocking is over and the new data is ready to read.  I can imagine slave select being used for this in normal mode, but that doesn't seem to be how it's supposed to be used and, in any event, it's not used at all in daisy-chain mode.  Thanks.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Does this help?

 

• Bit 7 – SPIF: SPI Interrupt Flag

When a serial transfer is complete, the SPIF Flag is set. An interrupt is generated if
SPIE in SPCR is set and global interrupts are enabled. If SS is an input and is driven low
when the SPI is in Master mode, this will also set the SPIF Flag. SPIF is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, the
SPIF bit is cleared by first reading the SPI Status Register with SPIF set, then accessing
the SPI Data Register (SPDR).
 

John Samperi

Ampertronics Pty. Ltd.

www.ampertronics.com.au

* Electronic Design * Custom Products * Contract Assembly

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Edit: John's answer was better than mine!

David

Last Edited: Sat. Jul 16, 2016 - 07:45 PM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Thanks, John.  So it sounds like, in daisy-chain mode, all the SS lines should be tied together and the master pulls it low to signal the end of a transfer.  All the slaves then read their data, so you just make sure to send existing data (or an idle command) to the ones you don't want to do anything, and new data to the one you want to do something, is that right?

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

and the master pulls it low to signal the end of a transfer.

/SS is active low, so the master pulls it low to >>start<< a transfer.  It pulls it high to end a transfer.

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

The other answers are all you need to know to use SPI in an application, but it sounds to me like you're asking how the MCU knows to raise an SPI interrupt, yeah?  If that's indeed what you're asking, it counts to 8.  After every 8 clocks a new byte has been shifted in/out; the send register is empty and the receive register is full.  So an interrupt fires and you setup the next byte to be transferred.  Toggling SS isn't actually required, but it will help guarantee the master and slave are in sync.

Last Edited: Sun. Jul 17, 2016 - 02:59 AM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

joeymorin: John's quote says, "If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag." Since SPIF indicates the end of a transfer, doesn't the quote say SS should be driven low to indicate the end of a transfer?

Last Edited: Sun. Jul 17, 2016 - 06:20 AM
  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

Rezer: Actually, I'm more interested in the slaves. How do they know when a transfer is complete? Sounds like they look at SPIF which is set by asserting SS. In my case, the master will know when it's done since I'll know how many slaves there are and that's how many bytes I'll send.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

My answer pertains to the slaves, as well as the master. The hardware SPI only deals in single bytes, so after sending or receiving 8 bits it's "done". If you want to send 32 bytes in a single transfer, you have to service the interrupts and keep filling in bytes until you're out of bytes to send, and the slaves have to buffer the bytes until they see a pattern that youve decided to use to end the transmission, or you can just make it a fixed length and decide to always stop after 32 bytes. Either way, it's beyond the scope of what the SPI hardware does automatically.

As far as the SS line being pulled low when it's an input, that's not something that should typically occur. It means something else is trying to take control of the bus, and any transmission in progress will be aborted. The interrupt fires to give you a chance to handle what is essentially an error condition.

  • 1
  • 2
  • 3
  • 4
  • 5
Total votes: 0

John's quote says, "If SS is an input and is driven low when the SPI is in Master mode, this will also set the SPIF Flag." Since SPIF indicates the end of a transfer, doesn't the quote say SS should be driven low to indicate the end of a transfer?

No.  That is when dealing with SPI Master, not SPI Slave.  The AVR's SPI peripheral is designed to be capable of multi-master operation.  With multi-master, there is always a risk that two masters will be driving the bus at the same time, leading to bus contention and possible device damage as one master drives MOSI or SCK high while another is driving low.

 

To prevent this, the AVR's SPI can be made to automatically switch from Master mode to Slave mode.  This is done by configuring /SS on the master as an input.  When another master wants to take control of the bus, it drives the current master's /SS low.  The current master switches to slave mode, and notifies software by way of the SPIF flag.

 

This does >>not<< describe your situation.  Your master should keep /SS as an output to prevent this.

 

Actually, I'm more interested in the slaves. How do they know when a transfer is complete? Sounds like they look at SPIF which is set by asserting SS. In my case, the master will know when it's done since I'll know how many slaves there are and that's how many bytes I'll send.

No.  Again, you are confusing the action of a Master when its /SS is configured as an input.

 

As @Rezer has mentioned, a slave (and a master, for that matter) 'knows' that a transfer is complete because SPIF becomes set.  The confusion may result from the fact that there are multiple ways in which SPIF can become set.  In the case of a slave, it becomes set when an 8-bit transfer is complete.  The /SS is used to tell the slave to start listening.  When low, it listens.  When high, it ignores.

 

 

 

 

I suggest you read, in detail, the >>entire<< section on the SPI peripheral.  It's all in there.

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

Last Edited: Sun. Jul 17, 2016 - 02:01 PM