Hi - I've been trying to work this out in my head... Let's say you have an IC that has a FET push/pull output. So I suspect that they have a complementary pair of FETs on the output - N-FET on the low side, P-FET on the high side, with their gate tied together. When their gates are at GND, the P-FET is on, and when their gates are at VDD, the N-FET is on. But what happens when their gates are at VDD/2? It seems to me that most likely both FETs will be partially on.
Or are the threshold voltages carefully tuned so that they're at about +-VDD/2? Or do they just try to switch that gate voltage really quickly so that the shoot through doesn't last for very long?