How do ICs with FET push/pull outputs avoid shoot through?

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Hi - I've been trying to work this out in my head... Let's say you have an IC that has a FET push/pull output. So I suspect that they have a complementary pair of FETs on the output - N-FET on the low side, P-FET on the high side, with their gate tied together. When their gates are at GND, the P-FET is on, and when their gates are at VDD, the N-FET is on. But what happens when their gates are at VDD/2? It seems to me that most likely both FETs will be partially on.

Or are the threshold voltages carefully tuned so that they're at about +-VDD/2? Or do they just try to switch that gate voltage really quickly so that the shoot through doesn't last for very long?

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You can solve it if the turn-off time is faster than the turn-on time.

Jim

 

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ka7ehk wrote:
You can solve it if the turn-off time is faster than the turn-on time.

Jim


Hi Jim - Is that a parameter that one has much control over? I had always assumed that the turn on/turn off time was almost instantaneous - is that not right?

Thanks,

-Michael

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For FETs, no. It depends on the Gate Charge parameter and the current used to add or remove this charge.

With FETs, you control the delay time by controlling the charging (and discharging) currents. You can make these asymmetrical so that one is faster than the other.

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!

 

 

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Well that is exactly why an input should not float. A floating input could cause even 10mA of current from VCC to GND via half-on FETs.

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ka7ehk wrote:
For FETs, no. It depends on the Gate Charge parameter and the current used to add or remove this charge.

With FETs, you control the delay time by controlling the charging (and discharging) currents. You can make these asymmetrical so that one is faster than the other.

Jim


Jim - then my question is still unanswered. My assumption is that the gates of the P-FET and N-FET are tied together. If that isn't the case - I'd be curious what is used - maybe a resistor in parallel with a diode to slow down turn on times?

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Bad assumption! They may be shown that way in the block diagram but rarely so inside.

I think you will find that there are active pull-up and pull-down current sources on each gate. Independent ones. Don't forget that transistors (and FETs) are nearly free in an IC. There are often MANY more than suggested by device block diagrams.

Jim

 

Until Black Lives Matter, we do not have "All Lives Matter"!