High Frequency PLL Clock, oh really?

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I was peakin around the attiny45's datasheet, trying to think of somthing cool to code (i was thinkin about makeing an attiny45 fuse resetter or somthin, thad be nice)

and I was lookin at the system clock options, and I stumbled onto the section for High Frequency PLL Clock.. ok lookin reading.. hmm.. internal 64 MHz clock can be used as system clock?

Quote:
There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator
for the use of the Peripheral Timer/Counter1 and for the system clock source... ...it is divided by four like
shown in Table 7-10. When this clock source is selected,

ok first of all... can the attiny45 even run that fast?

Quote:
– ATtiny25/45/85V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny25/45/85: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V

so not V, can?

but can I use the PLL clock and disabled the ckdiv8 fuse? or would the attiny blow up or somthing?

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Look on page 23 at section 7.1.5 Internal PLL for Fast Peripheral Clock Generation – CLKpck.

Quote:
The fast peripheral clock, or a clock prescaled from that, can be selected as the clock source for Timer/Counter1 or as a system clock.
The key is the system clock is prescaled from the 64 MHz PLL clock. Figure 7.2 shows the fixed divide by 4 prescaler (between the PLL 8X and CKSEL3:0 multiplexer), so 16 MHz is the fastest system clock you can get using the 64 MHz PLL clock. Section 23.3 Speed Grades shows that it will have to run at least 4.? Vcc (its hard to tell on the chart exactly how much below 4.5 volts 16 MHz is at). Timer/Counter1 can run at 64 MHz. The best reason I can think of for using the 16 MHz divided down from the PLL for the system clock is it will synchronize with the 64 MHz Timer/Counter1 edge transition timing. The ATtimy lower speed V parts will not run at 16 MHz, but you can divide the system clock down to where it can run.

The same figure 7.2 shows the prescaler located before the system clock. So, yes you still can use the system prescaler, but it will not change the PLL 8X Fast Peripheral Clock speed. You do not even have to enable or use the PLL unless you want to. The Timer/Counter1 prescaler selects the system clock or PCK 64/32 MHz clock with the PCKE bit in the PLLCSR register.

I couldn't find your exact quote in the ATtiny25/45/85 data sheet. Are you using the latest 2586J–AVR–12/06 revision?

Last Edited: Sun. Jan 28, 2007 - 06:20 AM
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The answer is in the exact paragraph you quoted, when used as the system clock it is divided by 4, which means it runs the AVR at 16 MHz.

Regards,
Steve A.

The Board helps those that help themselves.

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Ok - they are all set. Now all they have left to do is to simply obtain an process improvement so they can do away with the divide by 4 block!

--
"Why am I so soft in the middle when the rest of my life is so hard?"
-Paul Simon

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So even if I set ckdiv8 to 1 (unprogrammed) it is still /8... oh well.. still neat i guess :)

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Not correct. If you unprogram CKDIV8 the system clock will be at the full input frequency during AVR startup. So, if you are using the 64 MHz PLL which is divided by 4 down to 16 MHz for the system clock, you will get a 16 MHz system clock if CKDIV8 is not programmed and you leave the CLKPR register set to zero.

If you are using an ATtiny45V then you need to program CKDIV8 so it can startup with a system clock that is slow enough for the V part. After startup you can then change the CLKPR register to divide by 2 which will get you an 8 MHz system clock that the V part can use (assuming a 2.7 volt Vcc or higher).