I have an application where the uC programming lines are broken out to a diagnostics connector. However, as those lines are shared by the SPi bus during normal operation, those lines are toggling away at (relatively) high frequency. In order to minimise EMI, i would like to effectively disconnect the ISP lines when there is no programmer present (which is of course 99.99999% of the time).
So, can anyone see a reason not to put say a quad 3 state buffer (ie 74HCT125 or similar) between the ISP lines and the diagnostics connector?
If i connect the external "reset" line to the buffer enable pins, and pull that line up with a resistor to VCC, when there is no programmer present, the buffer will be in HiZ mode, but when a programmer pulls the external reset line down, it will enable the buffer, which will pull the internal reset line down, putting the uC into programming mode.
In programming mode, where the programmer is the SPI master, the following are inputs to the target uC: SCK, MOSI, RESET so would be wired with the buffer outputs to the uC
and MISO is an output from the target uC, so would be wired to the buffer input.
In this way, i think, the external lines to the diagnostic connector will sit low during normal operation? (they might need some high value pull downs to make sure they sit at a known voltage when the buffer is not enabled etc)