Has anyone interfaced with an AD7894?

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Hey guys. I have to interface with a AD7894 (using an FPGA so not really and AVR topic..)

Anyway, I'm reading the data sheet and the timing on the serial protocol makes absolutely zero sense to me. Normally Analog Devices writes the best data sheets and app. notes around but I think they missed the mark on this one.

However, it might just be my dim understanding and not their fault at all. Has anyone used one of these buggers. Or even can someone have a look at the timing diagram of the serial protocol and see if they can translate it to me? It's on page 8.

In particular the 't4' and 't5' numbers are a mystery to me. Taken to the extremes it would seem that it is possible for data to only be valid for just over 10ns!!! hmmm I've got to be missing something.

Go electric!
Happy electric car owner / builder

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Perhaps the numbers can be interpreted
in the following way:

Assume you use a symmetric clock with
maximum speed (T2=T3=31.25ns meaning 16MHz clock).

It may take up to 60ns=T4 for the data to
become valid after the falling clock-edge.

After the falling clock edge data stays stable for
at least 10ns=T5. So there is a minimum
window of -5ns and +10ns around the clock edge
in this case. That should be no problem for a
shift-register to clock in the data with the
falling clock edge.

If you use much slower clock, you may clock in
your data at the positive edge, with a wider margin.

Thats how I would interpret the numbers.

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your interpretation matches mine. However they repeatedly say you can take the data on either edge. Also, if this were truly the case, I bet an AVR (just trying to keep this topic..er um...topical) would not be able to see the data in such a short time...but I digress...

So, your meaning is the same as mine...it seems with a fast clock you read the current data bit on the falling edge of the NEXT clock. That is truly weird.

Well thanks ossi, I'll see what happens when the hardware gets here. I'm doing this in VHDL on an FPGA but I figured the bright folks here might best answer my question. Not to mention it could help a fellow AVR'r out if they have to talk to this chip.

If anyone else has an opinion on the data sheet I'd love to hear it. Seems kinda odd to me.

Go electric!
Happy electric car owner / builder

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I think about it in the following way:

Why can you cascade shift registers ?
Its because the data out of the first register
stays constant a little bit around the clock edge.

I think it probably would be possible to
clock the data into an AVR via SPI interface
at a high speed as long as you match the AVRs
"setup" and "hold" times.

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and I'm sure they meant for it to be interfaced to a SPI bus. But strictly speaking at high speed it will not work on SPI...strictly speaking. SPI does not have a mode where you can read data on the falling edge AND clock new data on the falling edge. yeah you could pretend that data is really being clocked on the rising edge but that isn't how the data sheet reads.

Go electric!
Happy electric car owner / builder