GPR mapped to Data Memory

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Hi,

I have just started reading the AVR datasheet. I have  a question about General Purpose Registers. Are they in the same memory block as I/O registers and the SRAM data space or instead a separate logic?  If the latter, what is the benefit for mapping them to Memory addresses: 0 to 31? My questions also holds for the I/O registers

 

Thank you

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The GPR are just dotted around among other SFRs. In traditional AVR (mega/tiny) there only were three GPIOR0 GPIOR1 and GPIOR2 so in a typical AVR you would see:

 

 

 

Where the GPIOR register "fill in the gaps" among some other registers. In this case only GPIOR0- sits in the 0x00..0x1F IO range so can be used with the SBI/CBI family of opcodes. The GPIOR1/GPIOR2 are higher so have the efficiency of IN/OUT being usable but SBII/CBI cannot be.

 

In later AVR (so everything from Xmega onwards) Atmel extended  this so that there are actually 16 of them and they are all in SBI/CBI range making them great for "bit variables".

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There are both the "General Purpose CPU registers" (R0-R31), and the "General Purpose IO registers"

 

The general purpose registers are convenient bit-addressable memory, IFF they're in the low-address space where SBI/CBI/SBIS/SBIC work.  This is the case on older chips, and newer chips.  On some of the middle-aged chips, some of the GPIOR registers got pushed into higher addresses; I'm not sure what those are good for.

 

Having the CPU registers appear as "memory" locations 0-31 had a couple of rare uses (probably especially on chips with no RAM?), but the newer chips don't do that any more, so it's probably best to avoid it.

 

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westfw wrote:
Having the CPU registers appear as "memory" locations 0-31 had a couple of rare uses (probably especially on chips with no RAM?), but the newer chips don't do that any more, so it's probably best to avoid it.
It was originally done in the first AVR that had NO RAM whatsoever. Your only storage was the 32 CPU registers so if you wanted something like an indexed data table or something (admittedly not very big!) then having the registers visible in the "RAM map" aided this. The AVRs maintained this even after they got some RAM through the traditional tiny and mega chips. But the idea was abandoned in Xmega and all recent "tiny"/"mega" are really Xmegas so they no longer have this.

 

Wonder which model of AVR you are talking about ?

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Thank you for your answers. Actually, I was referring to General Purpose Registers in Atmega8515. I/O registers seem to be integrated within the Data SRAM

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Oh well the 8515 is such an old model of AVR it actually predates GPIORn registers so I guess you did mean the CPU registers R0..R31 and yes, in these old AVRs they are mapped to the first 32 locations of "RAM" (which is actually why all the "IO  space" addresses are off by 32 = 0x20). It is, a I said, a historical thing - it maps the registers so that some/all (actually all would be real difficult) can be treated as if they were simply a block of RAM.

 

BTW I wonder why you are using 8515 in 2020? There are a whole lot more AVRs now and lots of them have some fancy new features that weren't even a twinkle in Atmel's eye back at the time of 8515.

 

If nothing else most folks might use some kind of Arduino board as a good introduction to AVR - while they have various chips the majority have ATmega328P which may well date from 2005 but it has more features than a really old design like 8515.

Last Edited: Wed. Sep 16, 2020 - 02:07 PM
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Thank you, Dawson for the advice :)

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