getting regular timer interrupts.

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For an application, I need regular timer interrupts. I thought I'd set the timer in "CTC" mode, (WGMx[3:0] = 0x04 or 0x0c), and catch the overflow interrupts.

Or don't overflows happen if the timer is in CTC mode?

To get things to work I enabled the OCR1B comparator and made it compare to the constant "20" so everytime the timer crosses the value 20, I now get a TIMER1_COMPB interrupt.

Here is my initialization code:

  OCR1A = 1000-1; // reload counter/interrupt at 16000 Hz. 

  TCCR1A = 0;
  TCCR1B = (1 << CS10) | (1 << WGM12); // Mode 4 CTC. 
  //TCCR1B = (1 << CS10); // Mode 4 CTC. 
  TCCR1C = 0;

  OCR1B = 20;

  //TIMSK1 = _BV (TOIE1);
  TIMSK1 = _BV (OCIE1B);

  EICRA = 0;
  EIMSK = 0; 
  pwm_on = 0;
  sei (); 

So with the TIMSK1 = TOIE1 I would've expected to receive TIMER1_OVF_vect interrupts, but those don't happen, and with the now uncommented TIMSK1 = .. OCIE1B I do get the compare B interrupts. It currently works this way, with an interrrupt every 1000 cycles, but I'd like to know why the original thought won't work.

(I've programmed microprocessors a lot 10 and 20 years ago, and I always had trouble with interrupts. Back then (8051, PIC and Intel '960) I always forgot to set some bit before interrupts would work. But with AVR I usually manage to correctly get interrupts on the first try. Great architecture AVR!).

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Quote:
Or don't overflows happen if the timer is in CTC mode?
No, they don't. You need to use the compare match interrupt.
Quote:
To get things to work, I enabled the OCR1B comparator and made it compare to the constant "20" so everytime the timer crosses the value 20, I now get a TIMER1_COMPB interrupt.
But isn't CTC mode set to clear with OCR1A? So why not use that compare interrupt?

Regards,
Steve A.

The Board helps those that help themselves.

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If you want an overflow interrupt run the timer in Normal mode.

-Krishna Balan S

-------------------------------------------------------------------------

"Heroes are ordinary people with extraordinary commitment"

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OK. Guys. Thanks!

It seems that I and Atmel disagree about what "overflow" means. In my vocabulary whenever the counter resets back to 0 is an overflow. I now understand that they use the "stricter" definition of "overflow" as in: goes past 0xffff.

Yes, using the OCR1A interrupt should work. Stupid I didn't think of that. (I was under a bit of pressure: Here, I wrote the code, lets test it together.... And then it didn't work. So I had to come up with a solution while the other guy had nothing to do...)

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...and all that is well documented in a nice table in the manual: it clearly shows under which conditions in which mode an overflow/compare match etc. will occur. So, the info is right under your fingertips ... ;-)

Einstein was right: "Two things are unlimited: the universe and the human stupidity. But i'm not quite sure about the former..."

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You mean the table 16-4 on page 132 of my atmega32U2 datasheet?

If I follow the top line (mode 0) it says top = 0xffff and TOVn flag set on MAX. 0xffff is the max in this mode so the overflow flag and the corresponding interrupt will happen when the counter hits 0xffff.

In mode 4 the value in OCR1A is the MAX, so it should set the overflow flag when it hits OCR1A.

This table clearly supports my initial interpretation that the interrupt should have happened when the counter resets back to 0.

What table are you looking at?

If you're not familiar with a chip, you could sit down and read the whole datasheet from beginning to end. Now, whereas I have something close to photographic memory, I can't memorize a 300+ page datasheet on one go. I need to use the datasheet as a reference book and look up the things I need when I need them. After being familiar with such a chip for a while and after having used say 80% of the features, you could start reading the datasheet beginning to end and filling in the gaps. In this case, I think I need timer1, and I went to chapter 16, "16-bit timer/counter 1".

Last Edited: Thu. Oct 7, 2010 - 09:52 AM
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Quote:

In mode 4 the value in OCR1A is the MAX, so it should set the overflow flag when it hits OCR1A.

Not the overflow - the compare match.

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Quote:
In my vocabulary whenever the counter resets back to 0 is an overflow.

that would have simplified things considerably.

in reality, they have designed this thing to be a count-up timer that somehow behaves like a count-up/count-down timer. most complicated than it needs to be but also provides more flexibility.

a trade-off I guess.

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Quote:
In mode 4 the value in OCR1A is the MAX
No, in mode 4 the value in OCR1A is TOP, not MAX. The tables defining these terms is very clear on what each term means, and the table describing the modes says that the TOV1 flag is set at MAX, not TOP, for mode 4 (and mode 12).

Regards,
Steve A.

The Board helps those that help themselves.