I'm looking at a prototype where I need a 25 MHz clock, and it seems like it should be easy to get that using one of the GCLK pins. But ... how?
Clearly PLL0 output is no help; that's 130 Mhz on NGW, divide-by-5 gives "a bit too fast". OSC0 is at 20 Mhz (and OSC1 is at 12 MHz). So neither is directly useful, but it should be easy to put either one through PLL1 (unused!) and get a frequency that's an integer multiple of 25 Mhz. The GCLK can then divide that.
Now NGW docs say that the RC filter on PLL1 is tuned for 80 MHz if fed from OSC0 ... not helpful. But that's with PLLDIV=4 giving 5 MHz input to the multiplier stage ...
So my first question: is it "safe" to just use PLLMUL=20 to get a 100 MHz output, instead of the 16 on that webpage? Then divide-by-4 will be just right for 25 MHz. (And divide-by-8 gives 12.5 MHz, also useful.) I expect the answer here to be "yes".
Leading to second question: clk_set_rate("pll1", 100MHz) will fail ... is anyone working on (Linux) hacks to make setting PLL rates behave? I can just hack it together of course. But if my current understanding is correct, a general solution should be possible ... which adjusts PLLMUL with only concerns about output range, and might even be able to tweak PLLDIV if it knew the constraints from the relevant board-specific RC filter.
And the third: If I hook PLL1 up to OSC1 (currently unused), what frequency is that RC filter going to be aiming for? Still 5 MHz?? When PLLDIV=3 that gives 4 MHz (a good match for those RC values??), then PLLMUL=25 gives the same 100 MHz output so GCLK divide-by-4 (or 8) works. I'd run the PLL tool Atmel mentions, but it doesn't work in OpenOffice 2.2 and so I can't get help that way.
(Also: similar questions for STK1002 ... although there the webpage has goofed up PLL0 and PLL1, since clearly it's PLL0 that outputs 140 MHz. I think it's just MUL and DIV and Fout that got swapped. If the 100MHz number is correct, GCLK there should be easy.)