GCC optimizing away critical ISR prologue / epilogue code

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I've been playing around with GCC on some of the Atmel ARM parts (SAM7 micros), and in that crowd there is a lot of talk about not going past optimization level 1 on modules containing interrupt handlers, specifically because there are "bugs" in GCC that optimizes away some critical parts of the prologue / epilogue code. They say that this is repeatedly broken and fixed with various GCC releases.

My question is why is this not an issue for AVR-GCC? Is there something fundamentally different? Or have these bugs in GCC long since been solved and these are just old words of wisdom from previously traumatized individuals? Thanks.

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AVR-GCC currently uses a fixed prologue in ISRs
that will never be optimized away. So it's not an
issue.

Jörg Wunsch

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