GCC 8.1

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GCC 8.1 was released May-2 with AVR GCC 8.1 into Arch Linux on May-8.

 

"Dare to be naïve." - Buckminster Fuller

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Free Software Foundation (FSF)

GNU Project

GCC 8 Release Series — Changes, New Features, and Fixes

https://gcc.gnu.org/gcc-8/changes.html

...

 

AVR

  • The AVR port now supports the following XMEGA-like devices:

    ATtiny212, ATtiny214, ATtiny412, ATtiny414, ATtiny416, ATtiny417, ATtiny814, ATtiny816, ATtiny817, ATtiny1614, ATtiny1616, ATtiny1617, ATtiny3214, ATtiny3216, ATtiny3217

    The new devices are listed under -mmcu=avrxmega3.

    • These devices see flash memory in the RAM address space, so that features like PROGMEM and __flash are not needed any more (as opposed to other AVR families for which read-only data will be located in RAM except special, non-standard features are used to locate and access such data). This requires that the compiler is used with Binutils 2.29 or newer so that read-only data will be located in flash memory.
    • A new command-line option -mshort-calls is supported. This option is used internally for multilib selection of the avrxmega3 variants. It is not an optimization option. Do not set it by hand.
  • The compiler now generates efficient interrupt service routine (ISR) prologues and epilogues. This is achieved by using the new AVR pseudo instruction__gcc_isr which is supported and resolved by the GNU assembler.
    • As the __gcc_isr pseudo-instruction will be resolved by the assembler, inline assembly is transparent to the process. This means that when inline assembly uses an instruction like INC that clobbers the condition code, then the assembler will detect this and generate an appropriate ISR prologue / epilogue chunk to save / restore SREG as needed.
    • A new command-line option -mno-gas-isr-prologues disables the generation of the __gcc_isr pseudo instruction. Any non-naked ISR will save and restore SREGtmp_reg and zero_reg, no matter whether the respective register is clobbered or used.
    • The feature is turned on per default for all optimization levels except for -O0 and -Og. It is explicitly enabled by means of option -mgas-isr-prologues.
    • Support has been added for a new AVR function attribute no_gccisr. It can be used to disable __gcc_isr pseudo instruction generation for individual ISRs.
    • This optimization is only available if GCC is configured with GNU Binutils 2.29 or newer; or at least with a version of Binutils that implements featurePR21683.
  • The compiler no more saves / restores registers in main; the effect is the same as if attribute OS_task was specified for main. This optimization can be switched off by the new command-line option -mno-main-is-OS_task.

 

...

"Dare to be naïve." - Buckminster Fuller

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"Dare to be naïve." - Buckminster Fuller

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The compiler now generates efficient interrupt service routine (ISR) prologues and epilogues.
This is achieved by using the new AVR pseudo instruction which is supported and resolved by the GNU assembler.

Is there a better explanation of how this works, somewhere?   I don't understand how this "pseudo-instruction" does its magic.

I found:

GAS implements a __gcc_isr pseudo-instruction which scans the code and emits parts of ISR prologue and epilogue.

__gcc_isr 1: GAS will replace it by an ISR prologue chunk (at most 6 insns).

__gcc_isr 2: GAS will replace it by an ISR epilogue chunk (at most 5 insns).

__gcc_isr 0, Rx:  Scan the code since the last prologue chunk and replace all encountered prologue and epilogue chunks by appropriate code. Rx is general purpose register.

But that "scan the code and replace" seems very un-assembler like?  Is this sort of "scan and replace with non-instructions" something accessible to, say, user macros?  (could I use it remove trailing unused vectors, for instance...)

 

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Well pretty much anything useful added to avr-gcc these days is always by Georg-Johan so contact him and ask.

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clawson wrote:
Well pretty much anything useful added to avr-gcc these days is always by Georg-Johan so contact him and ask.

 

And he also kindly posts mingw builds here: https://sourceforge.net/projects...

Maybe he will make a 8.1 build available soon.

 

edit: wait, this other guy already made a windows build: http://blog.zakkemble.co.uk/avr-...

Last Edited: Sun. May 13, 2018 - 08:12 PM
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El Tangas wrote:

edit: wait, this other guy already made a windows build: http://blog.zakkemble.co.uk/avr-...

This other guy managed to make the build in May 2017 surprise

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May be an artifact of the content management system.

Pressed 'View History' :

History

2018-05-07
CURRENT RELEASE
AVR-GCC updated to 8.1.0

"Dare to be naïve." - Buckminster Fuller

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Yeah, I check his site for builds from time to time and I'm pretty sure gcc-8.1.0 wasn't there last time I looked, about 2 months ago.

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Is there a better explanation of how this works, somewhere?   I don't understand how this "pseudo-instruction" does its magic. 

Well pretty much anything useful added to avr-gcc these days is always by Georg-Johan so contact him and ask.

He did make a post about this some months ago.  I'll see if I can find it.

 

EDIT:

https://www.avrfreaks.net/forum/avr-gcc-uselessly-saving-r24-isr

 

"Experience is what enables you to recognise a mistake the second time you make it."

"Good judgement comes from experience.  Experience comes from bad judgement."

"Wisdom is always wont to arrive late, and to be a little approximate on first possession."

"When you hear hoofbeats, think horses, not unicorns."

"Fast.  Cheap.  Good.  Pick two."

"We see a lot of arses on handlebars around here." - [J Ekdahl]

 

Last Edited: Sat. May 19, 2018 - 06:20 PM
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Any chance of a quick guide to using this with Atmel Studio, for the lazy people such as myself?

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Can't give you a quick guide just now but if you simply search "toolchain flavour" you should find everything you need to know. If you want "different compilers" you set each one up as a "flavour" and then you later select the flavour you want to use for any particular project.

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Actually, there is a tutorial in this forum: https://www.avrfreaks.net/forum/...

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Thanks guys, I will try it out.

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hi,

has anybody got a working set of linker scripts for the ATtiny 1 series (416 816 etc) for binutils/ld ?

 

My toolchain with GCC 9 is working fabulously, compiling Ada and all,  but the linker thinks its own thoughts

as to where to put things, and I do not see any template for this arch.

 

Cheers,

j.

 

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Lift them from Atmel's 5.4

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in here?

AVR 8-bit Toolchain 3.6.1 - Linux 64-bit

j.

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Yup
.
Or maybe just pick up a recent DFP. They have .atpack extensions but are really just .zip

Last Edited: Sat. Jun 23, 2018 - 07:47 PM
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I will download that then. The source code is a version behind and does not mention them.

 

thanks, enjoy your sunday.

j.

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Short-changed again!

 

Gcc support is there, like in the gnu distribution, but ld support is missing.

 

I will have a look in studio 7 if I can find something.

 

So my question stays.

j.

 

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All current device support is available in http://packs.download.atmel.com, however I think the ld script is in avr-libc or in binutils...

:: Morten

 

(yes, I work for Atmel, yes, I do this in my spare time, now stop sending PMs)

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Morten thanks for your concern.

 

I do have the latest pack for software spec (or header file) purposes, but there is no linker script there.

For Avr-libc I got a patch file for these mcu's but there is no linker script there either.

 

binutils/ld makes up the linker scripts at compile time on the basis of some templates,

but the latest git version has not got the template yet. Most likely because the ld script build system

does not cater for code that does not start at '0' in memory. So it needs a relatively major overhaul for 

attiny 1 and 0 series.

 

It is not a major deal to make up a script, but a proven script is preferable.

 

j.

 

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Atmel publish their sources as a GPL requirement so you should be able to get access to templates in their latest binutils source.
.
Maybe easier, if you have access to a Windows machine is to download and install recent AS7 release and just lift .x files

Last Edited: Sun. Jun 24, 2018 - 07:29 PM
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"Dare to be naïve." - Buckminster Fuller

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These devices see flash memory in the RAM address space,

On the flip side, could the compiler accidentally assign some ram variable array to the flash area? I'd assume no, but sometimes those are the oops that get you.

When in the dark remember-the future looks brighter than ever.   I look forward to being able to predict the future!

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avrcandies wrote:
the compiler accidentally
compilers and linkers are usually fairly deterministic and don't do things "accidentally". It would be possible, I guess for a human to create a linker script that was in error that told the linker the wrong rules for placement.

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GCC 8.2 was released 14-Jul'18 and FSF AVR GCC 8.2 made Arch Linux 29-Jul'18.

https://www.archlinux.org/packages/?q=avr-gcc

 

Edit: typos

 

"Dare to be naïve." - Buckminster Fuller

Last Edited: Tue. Aug 14, 2018 - 02:39 PM
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Thanks an awful lot for that. 

I did get it to work in my own way but I will certainly compare notes. 

Thanks again.

 

j.

 

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deiKruve wrote:
... compiling Ada and all, ...
For AVR?

If yes, willing to post that to the AVR-Ada devloper's mailing list?

https://sourceforge.net/p/avr-ada/mailman/avr-ada-devel/

Reasons :

  • visibility for the third AVR Ada toolchain [AdaCore GNAT Community (GPL), AdaCore GNAT Pro, FSF AVR GCC Ada (GPL run-time exception)]
  • AVR-Ada team's first targets are Arduino
  • forthcoming Arduino Uno WiFi Rev2 (megaAVR 0-series mega4809)

Thanks!

 

https://www.avrfreaks.net/forum/i-didnt-know-you-could-get-ada-avr

https://www.avrfreaks.net/forum/megaavr-0-series?page=1#comment-2470876

 

"Dare to be naïve." - Buckminster Fuller