Regarding the FPSLIC:
In the past I disabled global interrupts when accessing the FPGA I/O using the FISCR (out instruction) and the FISUX (in/out) instruction, and after that enabling the interrupts.
I then needed the interrupts to stay enabled all of the time. I removed the disabling and enabling of interrupts before and after the FISCR and FISUX in/out instructions.
Problem is now that if an interrupt occurs between the FISCR register access and the FISUX register access, the MCU will access (read/write) to the wrong FPGA I/O register and things will go haywire.
To ensure valid behaviour, I save the FISCR instuction of the stack when entering an interrupt and restoring it when exiting the interrupt (before the REI instruction).
Is this method sufficient enough to ensure valid FPGA I/O accces?