Few questions about Interrupts

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Hi everyone,

I have few questions about interrupts. I use ATmega169P.

1. If an logic change interrupt is triggered (say PCINT pin goes low to high), and if the context switching from main() to ISR takes 10usec,

a)what if the interrupt re-appears within 10usec?
b)what if some other interrupt comes DURING context switching (say timer0 expires when AVR was pushing variables in stack)?

2. During an ISR execution, if I dont explicitly cli() and sei(), how will AVR react to other interrupts? Are rest of the interrupts disabled till ISR is complete? While SERVICING PCINT ISR, if timer0 expires, how this is handled?

3. Is there anything like interrupt priority?

4. Is there something like interrupt queue? Say when PCINT ISR is serviced, timer0 expires, then INT0 gets an edge and another PCINT is triggered by key press. How this will be handled by AVR?

All of my questions are answered by some or other datasheet of AVR, and I would be happy if you could point me to correct source. Pardon me if these questions have already been asked before, and honestly, I did not search forum before posting this.

Thanks and regards,
Vignesh

Cheers,
Vignesh

If everything seems to be coming onto your way, then you are probably driving on a wrong lane..

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1a - The second interrupt will be lost if it happens before the first ISR starts. If the interrupt flag is cleared before the second interrupt happens (which is early in the interrupt handling process), then the second interrupt is handled after the first completes.
1b - The timer interrupt will be handled after the PCINT interrupt finishes

2 - Any interrupt automatically clears the global interrupt flag at start and sets it on exit.

3 - Not really. However, if more than one interrupt is triggered simultaneously, then the one with the lowest interrupt vector is serviced first

4 - This is answered by the above rules.

This is all explained in any AVR datasheet in the Interrupt and Reset and Interrupt handling sections, as well as the bit descriptions of the individual peripherals.

Regards,
Steve A.

The Board helps those that help themselves.

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Hey Vignesh,

i assume here you are using the C language in programming .. if you use assembly i will declare this in the answer also
1.

a) i assume when this case takes place, the first thing happen is disabling the global interrupts and this operation is atomic one. so the case that you are talking about hardly happen (note that this happen automatically if you are writing in C , while you MUST write it in case of assembly)
b) the second interrupt will not be served unless the first one is served first. and the context in this case takes place happens from ISR to another one. so i am not sure if it will take the same 10u.s. or not

2. if you are writing in C , then the compiler make it for you. if you are writing in assembly , you need to make it manually. (disable interrupts , save the context you may need , execute the ISR Code , and at the end you restore the old ones by PUSH and POP instructions and reti of course).

3. in AVR i don't think it is present (or specifically in the ATmega169P).

4. yes . but note that the delays of the interrupts will differ than the the sum of the ISR latency + ISR execution + saving the restoring the contexts ... as you wil add also the other ISR execution times in turn - i guesss you may try to validate this by making a UART ISR for example and put a long delay in it and try to make another interrupt and see what will happen by leds , LCD or any sort of output device.

By the way , i suggest you may read this post ,, i guess it is useful for your questions in case of i answered somethings wrong.

https://www.avrfreaks.net/index.p...

also there are a very expert guys here in the AVR , they will irrigate you with their great experience !!

Regards,

-- A.El-Saeed

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Well, the interrupt handling will not necessarily take 10us, it will take 7 clock cycles plus whatever clocks it needs to finish the opcode that the AVR was executing when the interrupt occurred (assuming that the global interrupt flag is set). I'm not really sure where within the 7 cycles the interrupt flag is cleared, but it is certainly within the first 4 (the other three are the jump to the ISR).

Regards,
Steve A.

The Board helps those that help themselves.

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Hi Steve and Saeed,

Thanks a bunch for a detailed reply for every point that I have raised. You have cleared every doubt of mine.

Best regards,
Vignesh

Cheers,
Vignesh

If everything seems to be coming onto your way, then you are probably driving on a wrong lane..