I'm tryng to bring up my first AVR design using external RAM and it's not going well. I'm using an ATMega8515 at 16 MHz with a Cypress 12ns SRAM and 74AHC573 latch. The problem appears to be that the AD0-7 lines are not stable for the specified 26.25 ns min. address valid time prior to ALE going low (see values 2 and 4 on p. 199 of the 02/03 data sheet). Most of the time the latch still manages to lock in the right address, but, obviously, it should work all the time. As I said, I don't think the problem is with the latch, because I can see the address values bouncing up and down during the supposedly valid window. In the attached JPEG, you can see the ALE pulse (labeled, 2nd trace from the top). The 2 vertical dashed lines are 26.4 ns apart, and are aligned with the falling edge of ALE. So, the address in the bottom half of the display should be stable between the dashed lines. This picture was taken with the bus keeper enabled, but I have the same problem with it disabled. Any suggestions would be greatly appreciated. Thanks.