Error handling for TWI

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#1
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Hi all,

this is (part of) my TWI ISR on a ATmega644 which acts as TWI slave:

#define TWCR_ENABLE         ((1<<TWIE)|(1<<TWEN))
#define TWCR_TWEA           ((1<<TWEA))
#define TWCR_TWSTO          ((1<<TWSTO))
#define TWCR_TWINT          ((1<<TWINT))
#define TWCR_TWINT_TWEA     ((1<<TWINT)|(1<<TWEA))


ISR( TWI_vect )
{
    switch (TWSR & 0xf8)
    {
[...]
        case TW_ST_LAST_DATA:
        case TW_SR_DATA_NACK:
        default:
//            TWCR = TWCR_ENABLE | TWCR_TWSTO;
            TWCR = 0;
            TWCR = TWCR_ENABLE | TWCR_TWINT_TWEA;
    }
}

The error handling is "disable TWI and renable it again". Previously, it has been to set the STOP bit in TWCR and enable interrupts and acknowledge again.

But with the old code eventually (after many reads) the data I2C bus locked up--i.e. the AVR slave held the data line low, and was not going to release it anymore.

My current error handling is a bit brute force, so here my question: is there a better way to handle bus errors safely and gracefully at the same time?

Cheers,
Thomas

pycrc -- a free CRC calculator and C source code generator

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Hai Thomas,
I suggest u to write code in non interrupt mode.
U can check instruction one by one,which gives easy debugging.
Svm Prasad

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Do you have an emulator? Setting a break point in the default case would tell you if it even goes to the default case during that error. I only have a stop command in my default case of the TWI ISR and I've never seen it hold the data line down. Maybe somehow your ISR code is getting stuck in a loop and not exiting.

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For the archive:

of course it was my error. I did not read the manual properly. The correct code is

ISR( TWI_vect )
{
    switch (TWSR & 0xf8)
    {
[...]
        case TW_ST_LAST_DATA:
        case TW_SR_DATA_NACK:
        default:
            TWCR = TWCR_ENABLE | TWCR_TWSTO | TWCR_TWINT_TWEA;
    }
} 

I.e. The STOP bit must be set together with the TWINT bit, and not in two separate steps as I did previously.

Thomas

pycrc -- a free CRC calculator and C source code generator

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Hi all !

 

let say that uC  RESETs at 2nd bit (or any other, doesn't matter) like in picture during TWI transfer.

 

I have to "manually rescue TWI"  with port bit banging on SCL and SDA.

 

 

How to do this?

 

 

Thank you, guys !

 

Attachment(s): 

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Wow, tacked on to a pretty old thread.

 

Anyway, this Analog Devices app note seems to discuss your question a bit.  Other Google hits as well...

http://www.analog.com/media/en/t...

Fr

equently the master, which is usually a microcontroller

or a gate array, will be interrupted in the middle of its

communication with an I

2

C slave and, upon return, fi

nd

a stuck bus. Initially this looks like a device problem, but

it is not. The slave is still waiting to send the remainder

of the data requested by the master. The problem is that

the master has forgotten where it was when it was inter-

rupted or reset. An extraneous reset on the processor will

generally create this condition, especially if the processor

cannot save its status. At this point, the slave will have

put the next bit out on the SDA line (because the SCL line

may have dropped to a low on reset) and awaits the next

clock on SCL. Of course the processor does not send it,

and as a result this slave just waits and waits. If the bit

the slave puts on the SDA line is a 0, the newly awakened

processor sees what appears to be a hung bus. The bus

is in a nonoperational mode; however, it is not due to the

slave. It is the processor’s fault for not fi

nishing the mes-

sage it started. ...

...and on to the next page "Solution 1: Clocking Through the Problem"

 

 

You can put lipstick on a pig, but it is still a pig.

I've never met a pig I didn't like, as long as you have some salt and pepper.

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[Re:]Wow, tacked on to a pretty old thread.

Yes, I didn't want to start a new topic.

 

Thank you for link !  

That's what I've been looking for ! 

 

Best regards !