I have a design that has data saved to EEPROM. Very occasionally, I noticed that the data has been corrupted. It has taken me ages to find the cause but I believe it is due to the ramp up/down speed of the power supply to the chip. If all program code that refers to the EE is stripped out (to avoid inadvertant read/write access to EE), the EE can still be messed up.
There is a 500A capable (!!!) thyristor driven crowbar trip circuit across the 5V rail to protect the safety critical design. The power can go from 5V to 0 in about 10us. Fast. Are there any documented failure modes of the EE due to power cycling? Is there an easy work around?
We've also noticed that if there are huge (100+Amp) switching currents near the chip (but not connected anywhere in the same circuit), the EE can also be corrupted, although the power supply 'looks' clean. This works within about a 1m radius. Blasting the circuit with 1000W ERP (rf) through a log-periodic at various frequencies on a bench has no effect.
I remember the good old days of 'tricking' petrol station pumps with CB radios... I can't believe that the AVR is still susceptible to this. The flash program memory, which is of similar silicon design/construction on the die is not affected at all. Even if there is no program code in the chip at all to read or write the EE, the data still gets corrupted (reading back through AVRISP). SRAM is not affected. Data registers are not affected. (Brown-out detection is active- I suspect that its not fast enough- takes 2 clks.)
[cliff: NB this has been moved by the OP (rightly) from GCC forum - but there was already one reply there: