I'm trying to understand the XMEGA E5 SPI peripheral's buffer modes. The manual states:
Buffered mode 2:
The SPI module is single buffered in the transmit direction and double buffered in the receive direction. A byte writ-
ten to the transmit register will be copied to the shift register when the SPI is enabled. Then, one SPI transfer must
be completed before the data is copied to the shift register.
That's not very clear to me. In mode 1 there is a dummy byte shifted out, and in mode 2 there isn't. But what does the third sentence mean, about one transfer being completed before data is copied to the shift register?
My guess is that it refers to reading bytes, as in you must wait for the first byte written to clear the FIFO before a byte is available to read.