Does BYTEMODE actually work?

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Hi,

Has anybody bothered to try the BYTEMODE that should be available in TC0 in the XMEGA AU controllers? It is barely mentioned in the manual, and doesn't seem to be mentioned in the datasheets at all. It is not clear if it is supposed to count up or down (I assumed down, since it seems to be a special case of split mode), but in my case, it doesn't seem to run at all. At least, it doesn't generate interrupts.

This is my (current) setup code:

  TCC2_CTRLA=0x00;  // Timer OFF
  TCC2_LCNT=0;
  TCC2_LPER=43;
  TCC2_CTRLB=0;
  TCC2_CTRLC=0;
  TCC2_CTRLE=1;     // 8 bit counter mode
  TCC2_INTCTRLA=0x00; // No interrupt
  TCC2_INTCTRLB=0;
  TCC2_CTRLA=0x05; // Timer ON; prescale 64

I use an xmega128A4U controller, which runs at 32 MHz. I expected that the "underflow" flag (LUNFIF) would be set every 88 µs. It never is. Just for debugging purposes, I monitor the interrupt flag with this code:

    if (bit_is_set(TCC2_INTFLAGS,TC2_LUNFIF_bp))
    {
      TCC2_INTFLAGS=TCC2_INTFLAGS;
      PORTA_OUTTGL=0x08;
    }

If I switch to normal mode, the interrupt flag works nicely, so somehow the BYTEMODE works very differently. Even if the counting direction was opposite, and it used all 16 bits, I should still get a reaction every 130 ms (which I do if I set TCC2_CTRLE=0; ).

So my conclusion is that either BYTEMODE works very differently from what I had expected, or it doesn't work at all.

By the way "“ split mode seems to work. Except that it doesn't seem to reload LPER. But at least it generates interrupts.

You're absolutely right. This member is stupid. Please help.

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It works for me.

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ErikT wrote:
It is barely mentioned in the manual, and doesn't seem to be mentioned in the datasheets at all. It is not clear if it is supposed to count up or down (I assumed down, since it seems to be a special case of split mode), but in my case, it doesn't seem to run at all.

Have you read Chapter 15: "TC2 – 16-bit Timer/Counter Type 2" in the AU manual? I think that it's very clear there that it counts down.

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I expect it counts up per default because

Quote:
01 BYTEMODE Upper byte of the counter (CNTH) will be set to zero after each counter clock cycle
10 SPLITMODE Timer/counter 0 is split into two 8-bit timer/counters (timer/counter type 2)

from this quote I would think OP should look at timer type 0 and use TCC0 registers except that the counter is only 8 bit.
/Lars

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Ok. Forget about what I said then, I was talking about split mode.

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Have you tried observing its behaviour in the simulator?